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Groups > linux.kernel > #1443855

[PATCH] spi: rockchip: limit transfers to (64K - 1) bytes

From Brian Norris <briannorris@chromium.org>
Newsgroups linux.kernel
Subject [PATCH] spi: rockchip: limit transfers to (64K - 1) bytes
Date 2016-07-15 03:40 +0200
Message-ID <rV0gF-qZ-5@gated-at.bofh.it> (permalink)
Organization linux.* mail to news gateway

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The Rockchip SPI controller's length register only supports 16-bits,
yielding a maximum length of 64KiB (the CTRLR1 register holds "length -
1"). Trying to transfer more than that (e.g., with a large SPI flash
read) will cause the driver to hang.

Now, it seems that while theoretically we should be able to program
CTRLR1 with 0xffff, and get a 64KiB transfer, but that also seems to
cause the core to choke, so stick with a maximum of 64K - 1 bytes --
i.e., 0xffff.

Signed-off-by: Brian Norris <briannorris@chromium.org>
---
 drivers/spi/spi-rockchip.c | 17 +++++++++++++++++
 1 file changed, 17 insertions(+)

diff --git a/drivers/spi/spi-rockchip.c b/drivers/spi/spi-rockchip.c
index d840324bcc9f..0f89c2169c24 100644
--- a/drivers/spi/spi-rockchip.c
+++ b/drivers/spi/spi-rockchip.c
@@ -142,6 +142,12 @@
 /* sclk_out: spi master internal logic in rk3x can support 50Mhz */
 #define MAX_SCLK_OUT		50000000
 
+/*
+ * SPI_CTRLR1 is 16-bits, so we should support lengths of 0xffff + 1. However,
+ * the controller seems to hang when given 0x10000, so stick with this for now.
+ */
+#define ROCKCHIP_SPI_MAX_TRANLEN		0xffff
+
 enum rockchip_ssi_type {
 	SSI_MOTO_SPI = 0,
 	SSI_TI_SSP,
@@ -573,6 +579,11 @@ static void rockchip_spi_config(struct rockchip_spi *rs)
 	dev_dbg(rs->dev, "cr0 0x%x, div %d\n", cr0, div);
 }
 
+static size_t rockchip_spi_max_transfer_size(struct spi_device *spi)
+{
+	return ROCKCHIP_SPI_MAX_TRANLEN;
+}
+
 static int rockchip_spi_transfer_one(
 		struct spi_master *master,
 		struct spi_device *spi,
@@ -589,6 +600,11 @@ static int rockchip_spi_transfer_one(
 		return -EINVAL;
 	}
 
+	if (xfer->len > ROCKCHIP_SPI_MAX_TRANLEN) {
+		dev_err(rs->dev, "Transfer is too long (%d)\n", xfer->len);
+		return -EINVAL;
+	}
+
 	rs->speed = xfer->speed_hz;
 	rs->bpw = xfer->bits_per_word;
 	rs->n_bytes = rs->bpw >> 3;
@@ -730,6 +746,7 @@ static int rockchip_spi_probe(struct platform_device *pdev)
 	master->prepare_message = rockchip_spi_prepare_message;
 	master->unprepare_message = rockchip_spi_unprepare_message;
 	master->transfer_one = rockchip_spi_transfer_one;
+	master->max_transfer_size = rockchip_spi_max_transfer_size;
 	master->handle_err = rockchip_spi_handle_err;
 
 	rs->dma_tx.ch = dma_request_chan(rs->dev, "tx");
-- 
2.8.0.rc3.226.g39d4020

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Thread

[PATCH] spi: rockchip: limit transfers to (64K - 1) bytes Brian Norris <briannorris@chromium.org> - 2016-07-15 03:40 +0200
  Re: [PATCH] spi: rockchip: limit transfers to (64K - 1) bytes Brian Norris <briannorris@chromium.org> - 2016-07-15 04:40 +0200
    Re: [PATCH] spi: rockchip: limit transfers to (64K - 1) bytes Shawn Lin <shawn.lin@rock-chips.com> - 2016-07-15 04:50 +0200
      Re: [PATCH] spi: rockchip: limit transfers to (64K - 1) bytes Brian Norris <briannorris@chromium.org> - 2016-07-15 05:10 +0200
  Applied "spi: rockchip: limit transfers to (64K - 1) bytes" to the spi tree Mark Brown <broonie@kernel.org> - 2016-07-20 18:50 +0200
    Re: Applied "spi: rockchip: limit transfers to (64K - 1) bytes" to  the spi tree Brian Norris <briannorris@chromium.org> - 2016-07-20 19:10 +0200

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