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Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute Read-allocate hints

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Hi Shanker,

On 12/07/16 04:36, Shanker Donthineni wrote:
> Read-allocation hints are not enabled for both the GIC-ITS and GICR
> tables. This forces the hardware to always read the table contents
> from an external memory (DDR) which is slow compared to cache memory.
> Most of the tables are often read by hardware. So, it's better to
> enable Read-allocate hints in addition to Write-allocate hints in
> order to improve the GICR_PEND, GICR_PROP, Collection, Device, and
> vCPU tables lookup time.

While I'm not opposed to such a change, I'd like to see some evidence
that this actually makes a difference. Have you measured an improvement
on a particular implementation? If so, could you share your benchmarking
method so that it could be be measured on others as well?

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...

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[PATCH] irqchip/gicv3-its: Enable cacheable attribute Read-allocate hints Shanker Donthineni <shankerd@codeaurora.org> - 2016-07-12 05:40 +0200
  Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute  Read-allocate hints Marc Zyngier <marc.zyngier@arm.com> - 2016-07-12 10:10 +0200
    Re: [PATCH] irqchip/gicv3-its: Enable cacheable attribute  Read-allocate hints Shanker Donthineni <shankerd@codeaurora.org> - 2016-07-12 15:40 +0200

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