Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing

From	Peter Zijlstra <peterz@infradead.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing
Date	2016-06-08 08:50 +0200
Message-ID	<rHFto-4Z9-45@gated-at.bofh.it> (permalink)
References	<rHCYx-3wB-1@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Wed, Jun 08, 2016 at 06:02:16AM +0200, Lukasz Odzioba wrote:
> For Knights Landing processor we need to filter OFFCORE_RESPONSE
> events by config1 parameter to make sure that it will end up in
> an appropriate PMC to meet specification.
> 
> On Knights Landing:
> MSR_OFFCORE_RSP_1 bits 8, 11, 14 can be used only on PMC1
> MSR_OFFCORE_RSP_0 bit 38 can be used only on PMC0
> 
> This patch introduces INTEL_EEVENT_CONSTRAINT where third parameter
> specifies extended config bits allowed only on given PMCs.
> 

How does this work in the light of intel_alt_er() ?

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[PATCH 1/1] perf/x86/intel: Add extended event constraints for Knights Landing Lukasz Odzioba <lukasz.odzioba@intel.com> - 2016-06-08 06:10 +0200
  Re: [PATCH 1/1] perf/x86/intel: Add extended event constraints for  Knights Landing Peter Zijlstra <peterz@infradead.org> - 2016-06-08 08:50 +0200

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