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Groups > linux.kernel > #1407737
| From | Boris Ostrovsky <boris.ostrovsky@oracle.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support |
| Date | 2016-05-27 00:10 +0200 |
| Message-ID | <rDbDA-3vK-13@gated-at.bofh.it> (permalink) |
| References | (1 earlier) <rvjyi-1lB-3@gated-at.bofh.it> <rvjyj-1lB-25@gated-at.bofh.it> <rCMvv-4LK-9@gated-at.bofh.it> <rD6kx-dV-11@gated-at.bofh.it> <rD6Nz-p8-21@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On 05/26/2016 12:55 PM, Boris Ostrovsky wrote:
> On 05/26/2016 12:26 PM, Jan Beulich wrote:
>>>>> Boris Ostrovsky <boris.ostrovsky@oracle.com> 05/25/16 9:17 PM >>>
>>> On 05/05/2016 12:58 AM, Lv Zheng wrote:
>>>> +static u8
>>>> +acpi_hw_get_access_bit_width(struct acpi_generic_address *reg, u8 max_bit_width)
>>>> +{
>>>> + u64 address;
>>>> +
>>>> + if (!reg->access_width) {
>>>> + /*
>>>> + * Detect old register descriptors where only the bit_width field
>>>> + * makes senses. The target address is copied to handle possible
>>>> + * alignment issues.
>>>> + */
>>>> + ACPI_MOVE_64_TO_64(&address, ®->address);
>>>> + if (!reg->bit_offset && reg->bit_width &&
>>>> + ACPI_IS_POWER_OF_TWO(reg->bit_width) &&
>>>> + ACPI_IS_ALIGNED(reg->bit_width, 8) &&
>>>> + ACPI_IS_ALIGNED(address, reg->bit_width)) {
>>>> + return (reg->bit_width);
>>>> + } else {
>>>> + if (reg->space_id == ACPI_ADR_SPACE_SYSTEM_IO) {
>>>> + return (32);
>>> This (together with "... Add access_width/bit_offset support in
>>> acpi_hw_write") breaks Xen guests using older QEMU which doesn't support
>>> 4-byte IO accesses.
>>>
>>> Why not return "reg->bit_width?:max_bit_width" ? This will preserve
>>> original behavior.
>> Did you figure out why we get here in the first place, instead of taking the
>> first "return"? I.e. isn't the issue the apparently wrong use of the second
>> ACPI_IS_ALIGNED() above? Afaict it ought to be
>> ACPI_IS_ALIGNED(address, reg->bit_width / 8)...
> We are trying to access address 0x...b004 (PM1a control) so yes, fixing
> alignment check would probably resolve the problem that we are seeing now.
>
> However, for compatibility purposes we may consider not doing any checks
> and simply return bit_width if access_width is not available.
Interestingly enough I bisected what I thought was a completely
different problem to this patch as well.
Something is messed up with 32-bit dom0 booting (so no QEMU) on one
machine in my pool. First error that I see is
pcieport 0000:00:02.0: can't find IRQ for PCI INT A; probably buggy
MP table
I'll look at this tomorrow, hopefully.
-boris
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Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-05-25 21:20 +0200
Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support "Jan Beulich" <jbeulich@suse.com> - 2016-05-26 18:30 +0200
Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-05-26 19:00 +0200
Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-05-27 00:10 +0200
RE: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support "Zheng, Lv" <lv.zheng@intel.com> - 2016-05-27 05:30 +0200
RE: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support "Zheng, Lv" <lv.zheng@intel.com> - 2016-05-27 09:40 +0200
Re: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support Boris Ostrovsky <boris.ostrovsky@oracle.com> - 2016-05-27 19:40 +0200
RE: [PATCH v2 08/13] ACPICA: Hardware: Add optimized access bit width support "Zheng, Lv" <lv.zheng@intel.com> - 2016-05-27 05:20 +0200
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