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Groups > linux.kernel > #1406309
| From | Javier Martinez Canillas <javier@osg.samsung.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 1/2] clk: exynos5420: Set ID for aclk333 gate clock |
| Date | 2016-05-24 19:50 +0200 |
| Message-ID | <rCoCS-6jw-27@gated-at.bofh.it> (permalink) |
| References | <rCoCS-6jw-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
The aclk333 clock needs to be ungated during the MFC power domain switch,
so set the clock ID to allow the Exynos power domain logic to lookup this
clock if is defined in the MFC PD device tree node.
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
---
drivers/clk/samsung/clk-exynos5420.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/clk/samsung/clk-exynos5420.c b/drivers/clk/samsung/clk-exynos5420.c
index 92382cef9f90..469bcae5de3a 100644
--- a/drivers/clk/samsung/clk-exynos5420.c
+++ b/drivers/clk/samsung/clk-exynos5420.c
@@ -946,7 +946,7 @@ static struct samsung_gate_clock exynos5x_gate_clks[] __initdata = {
GATE_BUS_TOP, 13, 0, 0),
GATE(0, "aclk166", "mout_user_aclk166",
GATE_BUS_TOP, 14, CLK_IGNORE_UNUSED, 0),
- GATE(0, "aclk333", "mout_user_aclk333",
+ GATE(CLK_ACLK333, "aclk333", "mout_user_aclk333",
GATE_BUS_TOP, 15, CLK_IGNORE_UNUSED, 0),
GATE(0, "aclk400_isp", "mout_user_aclk400_isp",
GATE_BUS_TOP, 16, 0, 0),
--
2.5.5
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[PATCH 0/2] ARM: dts: Fix imprecise external abort error when accessing Exynos MFC Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-24 19:50 +0200
[PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-24 19:50 +0200
Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-05-25 09:50 +0200
Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-05-25 10:10 +0200
Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-25 16:30 +0200
Re: [PATCH 2/2] ARM: dts: Add async-bridge clock to MFC power domain for Exynos5420 Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-05-30 09:50 +0200
[PATCH 1/2] clk: exynos5420: Set ID for aclk333 gate clock Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-24 19:50 +0200
Re: [PATCH 1/2] clk: exynos5420: Set ID for aclk333 gate clock Krzysztof Kozlowski <k.kozlowski@samsung.com> - 2016-05-25 09:20 +0200
Re: [PATCH 1/2] clk: exynos5420: Set ID for aclk333 gate clock Sylwester Nawrocki <s.nawrocki@samsung.com> - 2016-05-30 14:50 +0200
Re: [PATCH 0/2] ARM: dts: Fix imprecise external abort error when accessing Exynos MFC Marek Szyprowski <m.szyprowski@samsung.com> - 2016-05-25 09:00 +0200
Re: [PATCH 0/2] ARM: dts: Fix imprecise external abort error when accessing Exynos MFC Javier Martinez Canillas <javier@osg.samsung.com> - 2016-05-25 16:20 +0200
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