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Re: [PATCH v3 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states

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On Mon, May 23, 2016 at 08:48:41PM +0530, Shreyas B. Prabhu wrote:
> POWER ISA v3 defines a new idle processor core mechanism. In summary,
>  a) new instruction named stop is added.
>  b) new per thread SPR named PSSCR is added which controls the behavior
> 	of stop instruction.
> 
> Supported idle states and value to be written to PSSCR register to enter
> any idle state is exposed via ibm,cpu-idle-state-names and
> ibm,cpu-idle-state-psscr respectively. To enter an idle state,
> platform provided power_stop() needs to be invoked with the appropriate
> PSSCR value.
> 
> This patch adds support for this new mechanism in cpuidle powernv driver.
> 
> Cc: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
> Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
> Cc: linux-pm@vger.kernel.org
> Cc: Michael Ellerman <mpe@ellerman.id.au>
> Cc: Paul Mackerras <paulus@ozlabs.org>
> Cc: linuxppc-dev@lists.ozlabs.org
> Signed-off-by: Shreyas B. Prabhu <shreyas@linux.vnet.ibm.com>

Reviewed-by: Gautham R. Shenoy <ego@linux.vnet.ibm.com>

--
Thanks and Regards
gautham.

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[PATCH v3 8/9] cpuidle/powernv: Add support for POWER ISA v3 idle states "Shreyas B. Prabhu" <shreyas@linux.vnet.ibm.com> - 2016-05-23 17:20 +0200
  Re: [PATCH v3 8/9] cpuidle/powernv: Add support for POWER ISA v3  idle states Gautham R Shenoy <ego@linux.vnet.ibm.com> - 2016-05-24 12:40 +0200

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