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Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701

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Hi, YT:

Some comments below.

On Fri, 2016-05-20 at 23:05 +0800, yt.shen@mediatek.com wrote:
> From: YT Shen <yt.shen@mediatek.com>
> 
> This patch add support for the Mediatek MT2701 DISP subsystem.
> There is only one OVL engine in MT2701.
> 
> Signed-off-by: YT Shen <yt.shen@mediatek.com>
>  
> +static void mtk_ddp_mux_sel(void __iomem *config_regs,
> +			    enum mtk_ddp_comp_id cur, enum mtk_ddp_comp_id next)
> +{
> +	if (cur == DDP_COMPONENT_BLS && next == DDP_COMPONENT_DSI0) {
> +		writel_relaxed(BLS_TO_DSI_RDMA1_TO_DPI1,
> +			       config_regs + DISP_REG_CONFIG_OUT_SEL);
> +	}
> +}
> +

The function name 'mux' looks strange. The register written here
controls the single output selection. I prefer to rename it as
mtk_ddp_sout_sel().

>  
> -static const enum mtk_ddp_comp_id mtk_ddp_main[] = {
> +static const enum mtk_ddp_comp_id mtk_ddp_main_2701[] = {
> +	DDP_COMPONENT_OVL0,
> +	DDP_COMPONENT_RDMA0,
> +	DDP_COMPONENT_COLOR0,
> +	DDP_COMPONENT_BLS,
> +	DDP_COMPONENT_DSI0,
> +};
> +
> +static const enum mtk_ddp_comp_id mtk_ddp_ext_2701[] = {
> +	DDP_COMPONENT_OVL0,
> +	DDP_COMPONENT_DSI0,
> +};
> +

These two pipelines has the same component such as OVL0 and DSI0. I
think user program could not enable both crtc at the same time. Maybe
MT2701 has only one crtc, so you should modify initial flow to create
only one crtc for main display. Or it's typo for external display pipe,
please correct it.


Regards,
CK

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[RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 <yt.shen@mediatek.com> - 2016-05-20 17:10 +0200
  Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 CK Hu <ck.hu@mediatek.com> - 2016-05-23 11:20 +0200
    Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 YT Shen <yt.shen@mediatek.com> - 2016-05-27 09:30 +0200
  Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 Emil Velikov <emil.l.velikov@gmail.com> - 2016-05-27 11:40 +0200
    Re: [RFC v2 2/5] drm/mediatke: add support for Mediatek SoC MT2701 YT Shen <yt.shen@mediatek.com> - 2016-05-30 12:30 +0200

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