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Re: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine handling

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On Fri, Feb 26, 2016 at 07:33:51PM +0530, Kedareswara rao Appana wrote:
> The current driver allows user to queue up multiple segments
> on to a single transaction descriptor. User will submit this single desc
> and in the issue_pending() we decode multiple segments and submit to SG HW engine.
> We free up the allocated_desc when it is submitted to the HW.
> 
> Existing code prevents the user to prepare multiple trasactions at same time as
> we are overwrite with the allocated_desc.
> 
> The best utilization of HW SG engine would happen if we collate the pending
> list when we start dma this patch updates the same.

Applied all. It is usually advisable to do cover letter using --cover-letter
for multi patch series

-- 
~Vinod

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[PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine handling Kedareswara rao Appana <appana.durga.rao@xilinx.com> - 2016-02-26 15:10 +0100
  [PATCH v3 2/4] dmaengine: xilinx_vdma: Simplify spin lock handling Kedareswara rao Appana <appana.durga.rao@xilinx.com> - 2016-02-26 15:10 +0100
  Re: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine handling Vinod Koul <vinod.koul@intel.com> - 2016-03-03 16:30 +0100
    RE: [PATCH v3 1/4] dmaengine: xilinx_vdma: Improve SG engine  handling Appana Durga Kedareswara Rao <appana.durga.rao@xilinx.com> - 2016-03-03 17:30 +0100

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