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Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection

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> From: Yunhui Cui <B56489@freescale.com>
> To: <dwmw2@infradead.org>, <computersforpeace@gmail.com>,
> 	<han.xu@freescale.com>
> Cc: <linux-kernel@vger.kernel.org>, <linux-mtd@lists.infradead.org>,
> 	<linux-arm-kernel@lists.infradead.org>, <yao.yuan@nxp.com>, Yunhui
> Cui
> 	<yunhui.cui@nxp.com>
> Subject: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW
> 	protection
> Message-ID: <1456988044-37061-4-git-send-email-B56489@freescale.com>
> Content-Type: text/plain
> 
> From: Yunhui Cui <yunhui.cui@nxp.com>
> 
> For Micron family ,The status register write enable/disable bit, provides
> hardware data protection for the device.
> When the enable/disable bit is set to 1, the status register nonvolatile bits
> become read-only and the WRITE STATUS REGISTER operation will not
> execute.
> 
> Signed-off-by: Yunhui Cui <yunhui.cui@nxp.com>
> ---
>  drivers/mtd/spi-nor/spi-nor.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/mtd/spi-nor/spi-nor.c b/drivers/mtd/spi-nor/spi-nor.c
> index ed0c19c..917f814 100644
> --- a/drivers/mtd/spi-nor/spi-nor.c
> +++ b/drivers/mtd/spi-nor/spi-nor.c
> @@ -39,6 +39,7 @@
> 
>  #define SPI_NOR_MAX_ID_LEN	6
>  #define SPI_NOR_MAX_ADDR_WIDTH	4
> +#define SPI_NOR_MICRON_WRITE_ENABLE	0x7f
> 
>  struct flash_info {
>  	char		*name;
> @@ -1238,6 +1239,14 @@ int spi_nor_scan(struct spi_nor *nor, const char
> *name, enum read_mode mode)
>  		write_sr(nor, 0);
>  	}
> 
> +	if (JEDEC_MFR(info) == SNOR_MFR_MICRON) {
> +		ret = read_sr(nor);
> +		ret &= SPI_NOR_MICRON_WRITE_ENABLE;
> +
For Micron the status register write enable/disable bit, its default/factory value is disable.
Can here first check ,then program?
> +		write_enable(nor);
> +		write_sr(nor, ret);
> +	}
> +
>  	if (!mtd->name)
>  		mtd->name = dev_name(dev);
>  	mtd->priv = nor;

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Re: [PATCH v3 4/4] mtd: spi-nor: Disable Micron flash HW protection Bean Huo 霍斌斌 (beanhuo)   <beanhuo@micron.com> - 2016-03-03 14:50 +0100

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