Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1335876

Re: [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate()

Show all headers | View raw

Quoting Eric Anholt (2016-02-15 19:03:58)
> We were rolling this ourselves, but clk-divider can do it now.
> 
> Signed-off-by: Eric Anholt <eric@anholt.net>

Applied to clk-next.

Regards,
Mike

> ---
>  drivers/clk/bcm/clk-bcm2835.c | 13 ++-----------
>  1 file changed, 2 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/clk/bcm/clk-bcm2835.c b/drivers/clk/bcm/clk-bcm2835.c
> index 9f4df8f..353e438 100644
> --- a/drivers/clk/bcm/clk-bcm2835.c
> +++ b/drivers/clk/bcm/clk-bcm2835.c
> @@ -1060,16 +1060,7 @@ static long bcm2835_pll_divider_round_rate(struct clk_hw *hw,
>  static unsigned long bcm2835_pll_divider_get_rate(struct clk_hw *hw,
>                                                   unsigned long parent_rate)
>  {
> -       struct bcm2835_pll_divider *divider = bcm2835_pll_divider_from_hw(hw);
> -       struct bcm2835_cprman *cprman = divider->cprman;
> -       const struct bcm2835_pll_divider_data *data = divider->data;
> -       u32 div = cprman_read(cprman, data->a2w_reg);
> -
> -       div &= (1 << A2W_PLL_DIV_BITS) - 1;
> -       if (div == 0)
> -               div = 256;
> -
> -       return parent_rate / div;
> +       return clk_divider_ops.recalc_rate(hw, parent_rate);
>  }
>  
>  static void bcm2835_pll_divider_off(struct clk_hw *hw)
> @@ -1430,7 +1421,7 @@ bcm2835_register_pll_divider(struct bcm2835_cprman *cprman,
>         divider->div.reg = cprman->regs + data->a2w_reg;
>         divider->div.shift = A2W_PLL_DIV_SHIFT;
>         divider->div.width = A2W_PLL_DIV_BITS;
> -       divider->div.flags = 0;
> +       divider->div.flags = CLK_DIVIDER_MAX_AT_ZERO;
>         divider->div.lock = &cprman->regs_lock;
>         divider->div.hw.init = &init;
>         divider->div.table = NULL;
> -- 
> 2.7.0
> 

Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread

Thread

[PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Eric Anholt <eric@anholt.net> - 2016-02-16 04:10 +0100
  [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate() Eric Anholt <eric@anholt.net> - 2016-02-16 04:10 +0100
    Re: [PATCH 2/2] clk: bcm2835: Reuse CLK_DIVIDER_MAX_AT_ZERO for recalc_rate() Michael Turquette <mturquette@baylibre.com> - 2016-02-16 23:00 +0100
  Re: [PATCH 1/2] clk: bcm2835: Fix setting of PLL divider clock rates Michael Turquette <mturquette@baylibre.com> - 2016-02-16 23:00 +0100

csiph-web