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Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

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On 11/11/15 06:33, Bharat Kumar Gogada wrote:
> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> 
> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> ---
> Added logic to allocate contiguous hwirq in nwl_irq_domain_alloc function.
> Moved MSI functionality to separate functions.
> Changed error return values.
> ---
>  .../devicetree/bindings/pci/xilinx-nwl-pcie.txt    |   68 ++
>  drivers/pci/host/Kconfig                           |   16 +-
>  drivers/pci/host/Makefile                          |    1 +
>  drivers/pci/host/pcie-xilinx-nwl.c                 | 1062 ++++++++++++++++++++
>  4 files changed, 1144 insertions(+), 3 deletions(-)
>  create mode 100644 Documentation/devicetree/bindings/pci/xilinx-nwl-pcie.txt
>  create mode 100644 drivers/pci/host/pcie-xilinx-nwl.c
> 

[...]

> +static int nwl_pcie_enable_msi(struct nwl_pcie *pcie, struct pci_bus *bus)
> +{
> +	struct platform_device *pdev = to_platform_device(pcie->dev);
> +	struct nwl_msi *msi = &pcie->msi;
> +	unsigned long base;
> +	int ret;
> +
> +	mutex_init(&msi->lock);
> +
> +	/* Check for msii_present bit */
> +	ret = nwl_bridge_readl(pcie, I_MSII_CAPABILITIES) & MSII_PRESENT;
> +	if (!ret) {
> +		dev_err(pcie->dev, "MSI not present\n");
> +		ret = -EIO;
> +		goto err;
> +	}
> +
> +	/* Enable MSII */
> +	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> +			  MSII_ENABLE, I_MSII_CONTROL);
> +
> +	/* Enable MSII status */
> +	nwl_bridge_writel(pcie, nwl_bridge_readl(pcie, I_MSII_CONTROL) |
> +			  MSII_STATUS_ENABLE, I_MSII_CONTROL);
> +
> +	/* setup AFI/FPCI range */
> +	msi->pages = __get_free_pages(GFP_KERNEL, 0);
> +	base = virt_to_phys((void *)msi->pages);
> +	nwl_bridge_writel(pcie, lower_32_bits(base), I_MSII_BASE_LO);
> +	nwl_bridge_writel(pcie, upper_32_bits(base), I_MSII_BASE_HI);

BTW, you still haven't answered my question as to why you need to waste
a page of memory here, and why putting a device address doesn't work.

As this is (to the best of my knowledge) the only driver doing so, I'd
really like you to explain the rational behind this.

Thanks,

	M.
-- 
Jazz is not dead. It just smells funny...
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Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-16 16:20 +0100
  Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Ray Jui <rjui@broadcom.com> - 2015-11-16 23:10 +0100
    RE: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-17 06:00 +0100
      Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-17 10:30 +0100
        RE: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-17 14:30 +0100
          Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Marc Zyngier <marc.zyngier@arm.com> - 2015-11-17 15:00 +0100
            Re: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Ray Jui <rjui@broadcom.com> - 2015-11-17 17:30 +0100
              RE: [PATCH v8] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bharat Kumar Gogada <bharat.kumar.gogada@xilinx.com> - 2015-11-18 08:00 +0100

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