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[PATCH v4 31/32] scsi: hisi_sas: add fatal irq handler

From John Garry <john.garry@huawei.com>
Newsgroups linux.kernel
Subject [PATCH v4 31/32] scsi: hisi_sas: add fatal irq handler
Date 2015-11-16 14:40 +0100
Message-ID <qvsaL-7Us-45@gated-at.bofh.it> (permalink)
References <qvrHI-7IR-11@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Add handlers for fatal interrupts

Signed-off-by: John Garry <john.garry@huawei.com>
---
 drivers/scsi/hisi_sas/hisi_sas_v1_hw.c | 119 +++++++++++++++++++++++++++++++++
 1 file changed, 119 insertions(+)

diff --git a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
index a95259c..e29b7c7 100644
--- a/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
+++ b/drivers/scsi/hisi_sas/hisi_sas_v1_hw.c
@@ -1573,6 +1573,93 @@ static irqreturn_t cq_interrupt_v1_hw(int irq, void *p)
 	return IRQ_HANDLED;
 }
 
+static irqreturn_t fatal_ecc_int_v1_hw(int irq, void *p)
+{
+	struct hisi_hba *hisi_hba = p;
+	struct device *dev = &hisi_hba->pdev->dev;
+	u32 ecc_int = hisi_sas_read32(hisi_hba, SAS_ECC_INTR);
+
+	if (ecc_int & SAS_ECC_INTR_DQ_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("%s: Fatal DQ 1b ECC interrupt (0x%x)\n",
+		      dev_name(dev), ecc_err);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_DQ_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_DQ_ECC_ADDR) &
+				HGC_DQ_ECC_ADDR_BAD_MSK) >>
+				HGC_DQ_ECC_ADDR_BAD_OFF;
+
+		panic("%s: Fatal DQ RAM ECC interrupt @ 0x%08x\n",
+		      dev_name(dev), addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_IOST_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("%s: Fatal IOST 1b ECC interrupt (0x%x)\n",
+		      dev_name(dev), ecc_err);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_IOST_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_IOST_ECC_ADDR) &
+				HGC_IOST_ECC_ADDR_BAD_MSK) >>
+				HGC_IOST_ECC_ADDR_BAD_OFF;
+
+		panic("%s: Fatal IOST RAM ECC interrupt @ 0x%08x\n",
+		      dev_name(dev), addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_ITCT_ECCBAD_MSK) {
+		u32 addr = (hisi_sas_read32(hisi_hba, HGC_ITCT_ECC_ADDR) &
+				HGC_ITCT_ECC_ADDR_BAD_MSK) >>
+				HGC_ITCT_ECC_ADDR_BAD_OFF;
+
+		panic("%s: Fatal TCT RAM ECC interrupt @ 0x%08x\n",
+		      dev_name(dev), addr);
+	}
+
+	if (ecc_int & SAS_ECC_INTR_ITCT_ECC1B_MSK) {
+		u32 ecc_err = hisi_sas_read32(hisi_hba, HGC_ECC_ERR);
+
+		panic("%s: Fatal ITCT 1b ECC interrupt (0x%x)\n",
+		      dev_name(dev), ecc_err);
+	}
+
+	hisi_sas_write32(hisi_hba, SAS_ECC_INTR, ecc_int | 0x3f);
+
+	return IRQ_HANDLED;
+}
+
+static irqreturn_t fatal_axi_int_v1_hw(int irq, void *p)
+{
+	struct hisi_hba *hisi_hba = p;
+	struct device *dev = &hisi_hba->pdev->dev;
+	u32 axi_int = hisi_sas_read32(hisi_hba, ENT_INT_SRC2);
+	u32 axi_info = hisi_sas_read32(hisi_hba, HGC_AXI_FIFO_ERR_INFO);
+
+	if (axi_int & ENT_INT_SRC2_DQ_CFG_ERR_MSK)
+		panic("%s: Fatal DQ_CFG_ERR interrupt (0x%x)\n",
+		      dev_name(dev), axi_info);
+
+	if (axi_int & ENT_INT_SRC2_CQ_CFG_ERR_MSK)
+		panic("%s: Fatal CQ_CFG_ERR interrupt (0x%x)\n",
+		      dev_name(dev), axi_info);
+
+	if (axi_int & ENT_INT_SRC2_AXI_WRONG_INT_MSK)
+		panic("%s: Fatal AXI_WRONG_INT interrupt (0x%x)\n",
+		      dev_name(dev), axi_info);
+
+	if (axi_int & ENT_INT_SRC2_AXI_OVERLF_INT_MSK)
+		panic("%s: Fatal AXI_OVERLF_INT incorrect interrupt (0x%x)\n",
+		      dev_name(dev), axi_info);
+
+	hisi_sas_write32(hisi_hba, ENT_INT_SRC2, axi_int | 0x30000000);
+
+	return IRQ_HANDLED;
+}
+
 static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 	{"Bcast"},
 	{"Phy Up"},
@@ -1580,12 +1667,22 @@ static const char phy_int_names[HISI_SAS_PHY_INT_NR][32] = {
 };
 
 static const char cq_int_name[32] = "cq";
+static const char fatal_int_name[HISI_SAS_FATAL_INT_NR][32] = {
+	"fatal ecc",
+	"fatal axi"
+};
+
 static irq_handler_t phy_interrupts[HISI_SAS_PHY_INT_NR] = {
 	int_bcast_v1_hw,
 	int_phyup_v1_hw,
 	int_abnormal_v1_hw
 };
 
+static irq_handler_t fatal_interrupts[HISI_SAS_MAX_QUEUES] = {
+	fatal_ecc_int_v1_hw,
+	fatal_axi_int_v1_hw
+};
+
 static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
 {
 	struct device *dev = &hisi_hba->pdev->dev;
@@ -1646,6 +1743,28 @@ static int interrupt_init_v1_hw(struct hisi_hba *hisi_hba)
 		}
 	}
 
+	idx = (hisi_hba->n_phy * HISI_SAS_PHY_INT_NR) + hisi_hba->queue_count;
+	for (i = 0; i < HISI_SAS_FATAL_INT_NR; i++, idx++) {
+		irq = irq_of_parse_and_map(np, idx);
+		if (!irq) {
+			dev_err(dev, "irq init: could not map fatal interrupt %d\n",
+				idx);
+			return -ENOENT;
+		}
+		(void)snprintf(&int_names[idx * HISI_SAS_NAME_LEN],
+			       HISI_SAS_NAME_LEN,
+			       "%s %s:%d", dev_name(dev), fatal_int_name[i], i);
+		rc = devm_request_irq(dev, irq, fatal_interrupts[i], 0,
+				      &int_names[idx * HISI_SAS_NAME_LEN],
+				      hisi_hba);
+		if (rc) {
+			dev_err(dev,
+				"irq init: could not request fatal interrupt %d, rc=%d\n",
+				irq, rc);
+			return -ENOENT;
+		}
+	}
+
 	return 0;
 }
 
-- 
1.9.1

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Thread

[PATCH v4 00/32] HiSilicon SAS driver John Garry <john.garry@huawei.com> - 2015-11-16 14:10 +0100
  [PATCH v4 01/32] [SCSI] sas: centralise ssp frame information units John Garry <john.garry@huawei.com> - 2015-11-16 14:20 +0100
  [PATCH v4 06/32] scsi: hisi_sas: add HW DMA structures John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 17/32] scsi: hisi_sas: add v1 hw module init John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 11/32] scsi: hisi_sas: add phy SAS ADDR initialization John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 07/32] scsi: hisi_sas: allocate memories and create pools John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 08/32] scsi: hisi_sas: add hisi_sas_remove John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 04/32] scsi: hisi_sas: add scsi host registration John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 22/32] scsi: hisi_sas: add ssp command function John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 14/32] scsi: hisi_sas: add hisi sas device type John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 15/32] scsi: hisi_sas: add phy and port init John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 02/32] devicetree: bindings: scsi: HiSi SAS John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
    Re: [PATCH v4 02/32] devicetree: bindings: scsi: HiSi SAS Rob Herring <robh@kernel.org> - 2015-11-16 15:00 +0100
  [PATCH v4 05/32] scsi: hisi_sas: scan device tree John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 16/32] scsi: hisi_sas: add timer and spinlock init John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 10/32] scsi: hisi_sas: add cq structure initialization John Garry <john.garry@huawei.com> - 2015-11-16 14:30 +0100
  [PATCH v4 24/32] scsi: hisi_sas: add dev_found and dev_gone John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 27/32] scsi: hisi_sas: add smp protocol support John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 32/32] MAINTAINERS: add maintainer for HiSi SAS driver John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 13/32] scsi: hisi_sas: add hisi_hba workqueue John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 12/32] scsi: hisi_sas: set dev DMA mask John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 20/32] scsi: hisi_sas: add v1 hw interrupt init John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 29/32] scsi: hisi_sas: add tmf methods John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 23/32] scsi: hisi_sas: add cq interrupt handler John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 30/32] scsi: hisi_sas: add control phy handler John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 21/32] scsi: hisi_sas: add path from phyup irq to SAS framework John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 09/32] scsi: hisi_sas: add slot init code John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 25/32] scsi: hisi_sas: add abnormal irq handler John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 31/32] scsi: hisi_sas: add fatal irq handler John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 03/32] scsi: hisi_sas: add initial bare main driver John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 19/32] scsi: hisi_sas: add v1 HW initialisation code John Garry <john.garry@huawei.com> - 2015-11-16 14:40 +0100
  [PATCH v4 26/32] scsi: hisi_sas: add bcast interrupt handler John Garry <john.garry@huawei.com> - 2015-11-16 14:50 +0100
  [PATCH v4 28/32] scsi: hisi_sas: add scan finished and start John Garry <john.garry@huawei.com> - 2015-11-16 15:00 +0100
  [PATCH v4 18/32] scsi: hisi_sas: add v1 hardware register definitions John Garry <john.garry@huawei.com> - 2015-11-16 15:00 +0100

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