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[PATCH V4 01/26] coresight: etm3x: moving etm_readl/writel to header file

From Mathieu Poirier <mathieu.poirier@linaro.org>
Newsgroups linux.kernel
Subject [PATCH V4 01/26] coresight: etm3x: moving etm_readl/writel to header file
Date 2015-11-13 20:00 +0100
Message-ID <qurJN-1FS-29@gated-at.bofh.it> (permalink)
References <qurA6-1CA-9@gated-at.bofh.it>
Organization linux.* mail to news gateway

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Moving functions etm_readl/writel to file "coresight-etm.h"
so that the main ETM3x driver can be split in more than one
file.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm.h   | 29 +++++++++++++++++++++++++++
 drivers/hwtracing/coresight/coresight-etm3x.c | 29 ---------------------------
 2 files changed, 29 insertions(+), 29 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm.h b/drivers/hwtracing/coresight/coresight-etm.h
index b4481eb29304..34f7db881fa7 100644
--- a/drivers/hwtracing/coresight/coresight-etm.h
+++ b/drivers/hwtracing/coresight/coresight-etm.h
@@ -251,4 +251,33 @@ enum etm_addr_type {
 	ETM_ADDR_TYPE_START,
 	ETM_ADDR_TYPE_STOP,
 };
+
+static inline void etm_writel(struct etm_drvdata *drvdata,
+			      u32 val, u32 off)
+{
+	if (drvdata->use_cp14) {
+		if (etm_writel_cp14(off, val)) {
+			dev_err(drvdata->dev,
+				"invalid CP14 access to ETM reg: %#x", off);
+		}
+	} else {
+		writel_relaxed(val, drvdata->base + off);
+	}
+}
+
+static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
+{
+	u32 val;
+
+	if (drvdata->use_cp14) {
+		if (etm_readl_cp14(off, &val)) {
+			dev_err(drvdata->dev,
+				"invalid CP14 access to ETM reg: %#x", off);
+		}
+	} else {
+		val = readl_relaxed(drvdata->base + off);
+	}
+
+	return val;
+}
 #endif
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index d630b7ece735..c1dc095c3fb0 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -42,35 +42,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO);
 static int etm_count;
 static struct etm_drvdata *etmdrvdata[NR_CPUS];
 
-static inline void etm_writel(struct etm_drvdata *drvdata,
-			      u32 val, u32 off)
-{
-	if (drvdata->use_cp14) {
-		if (etm_writel_cp14(off, val)) {
-			dev_err(drvdata->dev,
-				"invalid CP14 access to ETM reg: %#x", off);
-		}
-	} else {
-		writel_relaxed(val, drvdata->base + off);
-	}
-}
-
-static inline unsigned int etm_readl(struct etm_drvdata *drvdata, u32 off)
-{
-	u32 val;
-
-	if (drvdata->use_cp14) {
-		if (etm_readl_cp14(off, &val)) {
-			dev_err(drvdata->dev,
-				"invalid CP14 access to ETM reg: %#x", off);
-		}
-	} else {
-		val = readl_relaxed(drvdata->base + off);
-	}
-
-	return val;
-}
-
 /*
  * Memory mapped writes to clear os lock are not supported on some processors
  * and OS lock must be unlocked before any memory mapped access on such
-- 
1.9.1

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Thread

[PATCH V4 00/26] Coresight integration with perf  Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 25/26] perf tools: making coresight PMU listable Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 24/26] perf tools: adding perf_session to *info_prive_size() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 07/26] coresight: moving PM runtime operations to core framework Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 10/26] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 18/26] coresight: adding operation mode for sink->enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 17/26] coresight: etb10: moving to local atomic operations Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 22/26] coresight: updating documentation to reflect integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 26/26] perf tools: adding coresight etm PMU record capabilities Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 23/26] perf tools: making function set_max_cpu_num() non static Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 20/26] coresight: etm-perf: new PMU driver for ETM tracers Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 21/26] coresight: introducing a global trace ID function Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 19:50 +0100
  [PATCH V4 03/26] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 06/26] coresight: associating path with session rather than tracer Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 08/26] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 15/26] coresight: etm3x: implementing perf_enable/disable() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 09/26] coresight: add API to get sink from path Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 12/26] coresight: etm3x: consolidating initial config Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 13/26] coresight: etm3x: implementing user/kernel mode tracing Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 01/26] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 14/26] coresight: etm3x: adding perf_get/set_config() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100
  [PATCH V4 11/26] coresight: etm3x: changing default trace configuration Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 20:00 +0100

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