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[PATCH V3 16/26] perf: changing pmu::setup_aux() parameter to include event

From Mathieu Poirier <mathieu.poirier@linaro.org>
Newsgroups linux.kernel
Subject [PATCH V3 16/26] perf: changing pmu::setup_aux() parameter to include event
Date 2015-11-11 23:30 +0100
Message-ID <qtM3V-lk-65@gated-at.bofh.it> (permalink)
References <qtLUd-hJ-3@gated-at.bofh.it>
Organization linux.* mail to news gateway

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For Coresight ETMv3/4 tracers the event carries information
about trace modes such as user or kernel space tracing and
whether tracing is allowed when operating in secure mode.

Since this information is to be embedded in the private
structure returned by setup_aux(),  changing the first
parameter to be of type struct perf_event * so that all
the necessary information can be conveyed.  Also changing
current customer of the API to reflect the modification.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 arch/x86/kernel/cpu/perf_event_intel_bts.c | 4 +++-
 arch/x86/kernel/cpu/perf_event_intel_pt.c  | 5 +++--
 include/linux/perf_event.h                 | 2 +-
 kernel/events/ring_buffer.c                | 2 +-
 4 files changed, 8 insertions(+), 5 deletions(-)

diff --git a/arch/x86/kernel/cpu/perf_event_intel_bts.c b/arch/x86/kernel/cpu/perf_event_intel_bts.c
index d1c0f254afbe..773600b2f313 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_bts.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_bts.c
@@ -68,10 +68,12 @@ static size_t buf_size(struct page *page)
 }
 
 static void *
-bts_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool overwrite)
+bts_buffer_setup_aux(struct perf_event *event, void **pages,
+		     int nr_pages, bool overwrite)
 {
 	struct bts_buffer *buf;
 	struct page *page;
+	int cpu = event->cpu;
 	int node = (cpu == -1) ? cpu : cpu_to_node(cpu);
 	unsigned long offset;
 	size_t size = nr_pages << PAGE_SHIFT;
diff --git a/arch/x86/kernel/cpu/perf_event_intel_pt.c b/arch/x86/kernel/cpu/perf_event_intel_pt.c
index 42169283448b..f8b881210648 100644
--- a/arch/x86/kernel/cpu/perf_event_intel_pt.c
+++ b/arch/x86/kernel/cpu/perf_event_intel_pt.c
@@ -863,10 +863,11 @@ static int pt_buffer_init_topa(struct pt_buffer *buf, unsigned long nr_pages,
  * Return:	Our private PT buffer structure.
  */
 static void *
-pt_buffer_setup_aux(int cpu, void **pages, int nr_pages, bool snapshot)
+pt_buffer_setup_aux(struct perf_event *event, void **pages,
+		    int nr_pages, bool snapshot)
 {
 	struct pt_buffer *buf;
-	int node, ret;
+	int node, ret, cpu = event->cpu;
 
 	if (!nr_pages)
 		return NULL;
diff --git a/include/linux/perf_event.h b/include/linux/perf_event.h
index 092a0e8a479a..0d9964b5ed4d 100644
--- a/include/linux/perf_event.h
+++ b/include/linux/perf_event.h
@@ -292,7 +292,7 @@ struct pmu {
 	/*
 	 * Set up pmu-private data structures for an AUX area
 	 */
-	void *(*setup_aux)		(int cpu, void **pages,
+	void *(*setup_aux)		(struct perf_event *event, void **pages,
 					 int nr_pages, bool overwrite);
 					/* optional */
 
diff --git a/kernel/events/ring_buffer.c b/kernel/events/ring_buffer.c
index 182bc30899d5..87171b700c77 100644
--- a/kernel/events/ring_buffer.c
+++ b/kernel/events/ring_buffer.c
@@ -522,7 +522,7 @@ int rb_alloc_aux(struct ring_buffer *rb, struct perf_event *event,
 			goto out;
 	}
 
-	rb->aux_priv = event->pmu->setup_aux(event->cpu, rb->aux_pages, nr_pages,
+	rb->aux_priv = event->pmu->setup_aux(event, rb->aux_pages, nr_pages,
 					     overwrite);
 	if (!rb->aux_priv)
 		goto out;
-- 
1.9.1

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Thread

[PATCH V3 00/26] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:20 +0100
  [PATCH V3 07/26] coresight: moving PM runtime operations to core framework Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 17/26] coresight: etb10: moving to local atomic operations Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 24/26] perf tools: adding perf_session to *info_prive_size() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 05/26] coresight: etm3x: implementing 'cpu_id()' API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 08/26] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 23/26] perf tools: making function set_max_cpu_num() non static Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 20/26] coresight: etm-perf: new PMU driver for ETM tracers Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 06/26] coresight: associating path with session rather than tracer Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 11/26] coresight: etm3x: changing default trace configuration Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 25/26] perf tools: making coresight PMU listable Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 12/26] coresight: etm3x: consolidating initial config Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 19/26] coresight: etb10: implementing AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 10/26] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 03/26] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 14/26] coresight: etm3x: adding perf_get/set_config() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 09/26] coresight: add API to get sink from path Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 16/26] perf: changing pmu::setup_aux() parameter to include event Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 18/26] coresight: adding operation mode for sink->enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 01/26] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 26/26] perf tools: adding coresight etm PMU record capabilities Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 21/26] coresight: introducing a global trace ID function Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  [PATCH V3 22/26] coresight: updating documentation to reflect integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-11 23:30 +0100
  Re: [PATCH V3 02/26] coresight: etm3x: moving sysFS entries to dedicated file Arnd Bergmann <arnd@arndb.de> - 2015-11-11 23:40 +0100
    Re: [PATCH V3 02/26] coresight: etm3x: moving sysFS entries to  dedicated file Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-13 17:20 +0100
      Re: [PATCH V3 02/26] coresight: etm3x: moving sysFS entries to dedicated file Arnd Bergmann <arnd@arndb.de> - 2015-11-13 17:30 +0100
  Re: [PATCH V3 00/26] Coresight integration with perf Alexander Shishkin <alexander.shishkin@linux.intel.com> - 2015-11-12 12:00 +0100

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