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[PATCH] x86/intel_cacheinfo: Fix LLC topology for AMD Fam17h systems

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On AMD Fam17h systems, the last level cache is not resident in
Northbridge. Therefore, we cannot assign cpu_llc_id to same
value as Node ID (as we have been doing currently)

We should rather look at the ApicID bits of the core to provide
us the last level cache ID info. Doing that here.

Signed-off-by: Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com>
---
 arch/x86/kernel/cpu/intel_cacheinfo.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/arch/x86/kernel/cpu/intel_cacheinfo.c b/arch/x86/kernel/cpu/intel_cacheinfo.c
index e38d338..897a483 100644
--- a/arch/x86/kernel/cpu/intel_cacheinfo.c
+++ b/arch/x86/kernel/cpu/intel_cacheinfo.c
@@ -636,6 +636,9 @@ static int find_num_cache_leaves(struct cpuinfo_x86 *c)
 
 void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 {
+	unsigned int cpu = c->cpu_index;
+	unsigned int apicid = c->apicid;
+	unsigned int socket_id, core_complex_id;
 
 	if (cpu_has_topoext) {
 		num_cache_leaves = find_num_cache_leaves(c);
@@ -645,6 +648,17 @@ void init_amd_cacheinfo(struct cpuinfo_x86 *c)
 		else
 			num_cache_leaves = 3;
 	}
+
+	/*
+	 * Fix percpu cpu_llc_id here as LLC topology is different
+	 * for Fam17h systems.
+	 */
+	 if (c->x86 != 0x17 || !cpuid_edx(0x80000006))
+		return;
+
+	socket_id = (apicid >> c->x86_coreid_bits) - 1;
+	core_complex_id = (apicid & ((1 << c->x86_coreid_bits) - 1)) >> 3;
+	per_cpu(cpu_llc_id, cpu) = (socket_id << 3) | core_complex_id;
 }
 
 unsigned int init_intel_cacheinfo(struct cpuinfo_x86 *c)
-- 
2.6.1

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[PATCH] x86/intel_cacheinfo: Fix LLC topology for AMD Fam17h systems Aravind Gopalakrishnan <Aravind.Gopalakrishnan@amd.com> - 2015-11-03 20:20 +0100
  Re: [PATCH] x86/intel_cacheinfo: Fix LLC topology for AMD Fam17h  systems kbuild test robot <lkp@intel.com> - 2015-11-03 20:30 +0100
    Re: [PATCH] x86/intel_cacheinfo: Fix LLC topology for AMD Fam17h  systems Borislav Petkov <bp@alien8.de> - 2015-11-03 21:00 +0100

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