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RE: [PATCH v2] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC

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> -----Original Message-----
> From: Arnd Bergmann [mailto:arnd@arndb.de]
> Sent: Thursday, October 29, 2015 4:49 PM
> To: linux-arm-kernel@lists.infradead.org
> Cc: Rivera Jose-B46482; robh+dt@kernel.org; mark.rutland@arm.com; devicetree@vger.kernel.org; linux-
> kernel@vger.kernel.org; Sharma Bhupesh-B45370; Li Yang-Leo-R58472; Yoder Stuart-B08248
> Subject: Re: [PATCH v2] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC
> 
> On Wednesday 28 October 2015 16:09:44 J. German Rivera wrote:
> > +       rst_ccsr: rstccsr@1E60000 {
> > +               compatible = "syscon";
> > +               reg = <0x0 0x1E60000 0x0 0x10000>;
> > +       };
> > +
> >
> 
> What does 'rstccsr' stand for? Is this by chance a reset controller?

It is a region of some miscellaneous registers, some related to reset.
 
> If so, we probably want a real driver for it rather than just a
> syscon.

There is not other stuff in this region that to be exposed,
and so we really don't need a real driver.

My suggestion is to perhaps make that more explicit in the proposed
device tree node, by making the reg size "4" and naming it
as per the register name

       rstcr: rstcr@1E60000 {
               compatible = "syscon";
               reg = <0x0 0x1E60000 0x0 0x4>;
       };

The intent is really just to expose a single reset register
and use syscon-reboot until PSCI is available.

Thanks,
Stuart
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Re: [PATCH v2] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC Arnd Bergmann <arnd@arndb.de> - 2015-10-29 22:50 +0100
  RE: [PATCH v2] arm64: dts: Added syscon-reboot node for FSL's LS2085A  SoC Stuart Yoder <stuart.yoder@freescale.com> - 2015-10-30 17:40 +0100
    Re: [PATCH v2] arm64: dts: Added syscon-reboot node for FSL's LS2085A SoC Arnd Bergmann <arnd@arndb.de> - 2015-10-30 21:00 +0100

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