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[PATCH v2 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver

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From: Liu Ying <Ying.liu@freescale.com>

This patch adds device tree bindings for Synopsys DesignWare MIPI DSI
host controller DRM bridge driver.

Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
---

Changes in v2: None

 .../devicetree/bindings/drm/bridge/dw_mipi_dsi.txt | 76 ++++++++++++++++++++++
 1 file changed, 76 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt

diff --git a/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
new file mode 100644
index 0000000..bb87466
--- /dev/null
+++ b/Documentation/devicetree/bindings/drm/bridge/dw_mipi_dsi.txt
@@ -0,0 +1,76 @@
+Device-Tree bindings for Synopsys DesignWare MIPI DSI host controller
+
+The controller is a digital core that implements all protocol functions
+defined in the MIPI DSI specification, providing an interface between
+the system and the MIPI DPHY, and allowing communication with a MIPI DSI
+compliant display.
+
+Required properties:
+ - #address-cells: Should be <1>.
+ - #size-cells: Should be <0>.
+ - compatible: The first compatible string should be "fsl,imx6q-mipi-dsi"
+   for i.MX6q/sdl SoCs.  For other SoCs, please refer to their specific
+   device tree binding documentations.  A common compatible string
+   "snps,dw-mipi-dsi" should be appended for all SoCs.
+ - reg: Represent the physical address range of the controller.
+ - interrupts: Represent the controller's interrupt to the CPU(s).
+ - clocks, clock-names: Phandles to the controller's pll reference
+   clock(ref), configuration clock(cfg) and APB clock(pclk), as
+   described in [1].
+
+For more required properties, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+Required sub-nodes:
+ - A node to represent a DSI peripheral as described in [2].
+
+For more required sub-nodes, please refer to relevant device tree binding
+documentations which describe the controller embedded in specific SoCs.
+
+[1] Documentation/devicetree/bindings/clock/clock-bindings.txt
+[2] Documentation/devicetree/bindings/mipi/dsi/mipi-dsi-bus.txt
+
+example:
+	gpr: iomuxc-gpr@020e0000 {
+		/* ... */
+	};
+
+	mipi_dsi: mipi@021e0000 {
+		#address-cells = <1>;
+		#size-cells = <0>;
+		compatible = "fsl,imx6q-mipi-dsi", "snps,dw-mipi-dsi";
+		reg = <0x021e0000 0x4000>;
+		interrupts = <0 102 IRQ_TYPE_LEVEL_HIGH>;
+		gpr = <&gpr>;
+		clocks = <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+			 <&clks IMX6QDL_CLK_MIPI_CORE_CFG>,
+			 <&clks IMX6QDL_CLK_MIPI_IPG>;
+		clock-names = "ref", "cfg", "pclk";
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				mipi_mux_0: endpoint {
+					remote-endpoint = <&ipu1_di0_mipi>;
+				};
+			};
+
+			port@1 {
+				reg = <1>;
+
+				mipi_mux_1: endpoint {
+					remote-endpoint = <&ipu1_di1_mipi>;
+				};
+			};
+		};
+
+		panel {
+			compatible = "truly,tft480800-16-e-dsi";
+			reg = <0>;
+			/* ... */
+		};
+	};
-- 
2.6.2

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Thread

[PATCH v2 00/13] Add mipi dsi support for rk3288 Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
  [PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
    Re: [PATCH v2 12/13] drm/panel: simple: Add simple panel device tree binding Rob Herring <robh+dt@kernel.org> - 2015-11-02 16:10 +0100
      Re: [PATCH v2 12/13] drm/panel: simple: Add simple panel device tree  binding Chris Zhong <zyw@rock-chips.com> - 2015-11-03 01:30 +0100
  [PATCH v2 02/13] clk: rockchip: add mipidsi clocks on rk3288 Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
  [PATCH v2 05/13] Documentation: dt-bindings: Add bindings for Synopsys DW MIPI DSI DRM bridge driver Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
    Re: [PATCH v2 05/13] Documentation: dt-bindings: Add bindings for  Synopsys DW MIPI DSI DRM bridge driver Rob Herring <robh@kernel.org> - 2015-11-06 03:30 +0100
  [PATCH v2 07/13] drm: rockchip: Support Synopsys DesignWare MIPI DSI host controller Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
  [PATCH v2 10/13] of: add vendor prefix for boe Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
    Re: [PATCH v2 10/13] of: add vendor prefix for boe Rob Herring <robh+dt@kernel.org> - 2015-11-03 03:30 +0100
  [PATCH v2 01/13] clk: rockchip: add id for mipidsi sclk on rk3288 Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
  [PATCH v2 08/13] Documentation: dt-bindings: Add bindings for rk3288 DW MIPI DSI driver Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
    Re: [PATCH v2 08/13] Documentation: dt-bindings: Add bindings for  rk3288 DW MIPI DSI driver Rob Herring <robh@kernel.org> - 2015-11-06 03:20 +0100
  [PATCH v2 04/13] drm/dsi: Add a helper to get bits per pixel of MIPI DSI pixel format Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100
  [PATCH v2 06/13] drm/bridge: Add Synopsys DesignWare MIPI DSI host controller driver Chris Zhong <zyw@rock-chips.com> - 2015-10-31 14:00 +0100

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