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Groups > linux.kernel > #1246173
| From | Jon Mason <jonmason@broadcom.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [RFC 2/5] ARM: dts: enable clock support for Broadcom NSP |
| Date | 2015-10-13 23:30 +0200 |
| Message-ID | <qjfiY-1XD-49@gated-at.bofh.it> (permalink) |
| References | <qjfiW-1XD-9@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
Replace current device tree dummy clocks with real clock support for
Broadcom Northstar Plus SoC
Signed-off-by: Jon Mason <jonmason@broadcom.com>
---
arch/arm/boot/dts/bcm-nsp.dtsi | 93 ++++++++++++++++++++++++++++++++----------
1 file changed, 72 insertions(+), 21 deletions(-)
diff --git a/arch/arm/boot/dts/bcm-nsp.dtsi b/arch/arm/boot/dts/bcm-nsp.dtsi
index 58aca27..768ee24 100644
--- a/arch/arm/boot/dts/bcm-nsp.dtsi
+++ b/arch/arm/boot/dts/bcm-nsp.dtsi
@@ -32,6 +32,7 @@
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/clock/bcm-nsp.h>
#include "skeleton.dtsi"
@@ -42,7 +43,7 @@
mpcore {
compatible = "simple-bus";
- ranges = <0x00000000 0x19020000 0x00003000>;
+ ranges = <0x00000000 0x19000000 0x00023000>;
#address-cells = <1>;
#size-cells = <1>;
@@ -58,27 +59,34 @@
};
};
- L2: l2-cache {
- compatible = "arm,pl310-cache";
- reg = <0x2000 0x1000>;
- cache-unified;
- cache-level = <2>;
+ a9pll: arm_clk@0000 {
+ #clock-cells = <0>;
+ compatible = "brcm,nsp-armpll";
+ clocks = <&osc>;
+ reg = <0x0000 0x1000>;
+ };
+
+ timer@20200 {
+ compatible = "arm,cortex-a9-global-timer";
+ reg = <0x20200 0x100>;
+ interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&periph_clk>;
};
- gic: interrupt-controller@19021000 {
+ gic: interrupt-controller@21000 {
compatible = "arm,cortex-a9-gic";
#interrupt-cells = <3>;
#address-cells = <0>;
interrupt-controller;
- reg = <0x1000 0x1000>,
- <0x0100 0x100>;
+ reg = <0x21000 0x1000>,
+ <0x20100 0x100>;
};
- timer@19020200 {
- compatible = "arm,cortex-a9-global-timer";
- reg = <0x0200 0x100>;
- interrupts = <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH>;
- clocks = <&periph_clk>;
+ L2: l2-cache {
+ compatible = "arm,pl310-cache";
+ reg = <0x22000 0x1000>;
+ cache-unified;
+ cache-level = <2>;
};
};
@@ -87,33 +95,76 @@
#size-cells = <1>;
ranges;
- periph_clk: periph_clk {
+ osc: oscillator {
+ #clock-cells = <0>;
compatible = "fixed-clock";
+ clock-frequency = <25000000>;
+ };
+
+ iprocmed: iprocmed {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <2>;
+ clock-mult = <1>;
+ };
+
+ iprocslow: iprocslow {
#clock-cells = <0>;
- clock-frequency = <500000000>;
+ compatible = "fixed-factor-clock";
+ clocks = <&genpll BCM_NSP_GENPLL_IPROCFAST_CLK>;
+ clock-div = <4>;
+ clock-mult = <1>;
+ };
+
+ periph_clk: periph_clk {
+ #clock-cells = <0>;
+ compatible = "fixed-factor-clock";
+ clocks = <&a9pll>;
+ clock-div = <2>;
+ clock-mult = <1>;
};
};
axi {
compatible = "simple-bus";
- ranges = <0x00000000 0x18000000 0x00001000>;
+ ranges = <0x00000000 0x18000000 0x0003f164>;
#address-cells = <1>;
#size-cells = <1>;
- uart0: serial@18000300 {
+ uart0: serial@00300 {
compatible = "ns16550a";
- reg = <0x0300 0x100>;
+ reg = <0x00300 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <62499840>;
status = "disabled";
};
- uart1: serial@18000400 {
+ uart1: serial@00400 {
compatible = "ns16550a";
- reg = <0x0400 0x100>;
+ reg = <0x00400 0x100>;
interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
clock-frequency = <62499840>;
status = "disabled";
};
+
+ lcpll0: lcpll0@3f100 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-lcpll0";
+ reg = <0x3f100 0x14>;
+ clocks = <&osc>;
+ clock-output-names = "lcpll0", "pcie_phy", "sdio",
+ "ddr_phy";
+ };
+
+ genpll: genpll@3f140 {
+ #clock-cells = <1>;
+ compatible = "brcm,nsp-genpll";
+ reg = <0x3f140 0x24>;
+ clocks = <&osc>;
+ clock-output-names = "genpll", "phy", "ethernetclk",
+ "usbclk", "iprocfast", "sata1",
+ "sata2";
+ };
};
};
--
1.9.1
--
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Back to linux.kernel | Previous | Next — Previous in thread | Find similar | Unroll thread
[PATCH 0/5] ARM: dts: add device tree support for NS, NSP, and NS2 clocks Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
[RFC 3/5] ARM: dts: enable clock support for BCM5301X Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
[RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding Ray Jui <rjui@broadcom.com> - 2015-10-14 00:30 +0200
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding Jon Mason <jonmason@broadcom.com> - 2015-10-14 17:50 +0200
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding Ray Jui <rjui@broadcom.com> - 2015-10-14 19:00 +0200
Re: [RFC 4/5] clk: iproc: define Broadcom NS2 iProc clock binding Stephen Boyd <sboyd@codeaurora.org> - 2015-10-17 00:20 +0200
[RFC 5/5] ARM: dts: enable clock support for Broadcom NS2 Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
[RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding Ray Jui <rjui@broadcom.com> - 2015-10-14 00:20 +0200
Re: [RFC 1/5] clk: iproc: define Broadcom NSP iProc clock binding Jon Mason <jonmason@broadcom.com> - 2015-10-14 17:50 +0200
[RFC 2/5] ARM: dts: enable clock support for Broadcom NSP Jon Mason <jonmason@broadcom.com> - 2015-10-13 23:30 +0200
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