Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]


Groups > linux.kernel > #1242559

Re: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode

Path csiph.com!eternal-september.org!feeder.eternal-september.org!aioe.org!bofh.it!news.nic.it!robomod
From Catalin Marinas <catalin.marinas@arm.com>
Newsgroups linux.kernel
Subject Re: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode
Date Thu, 08 Oct 2015 18:00:01 +0200
Message-ID <qhlLP-81t-7@gated-at.bofh.it> (permalink)
References <qfbxf-od-5@gated-at.bofh.it>
X-Original-To Marc Zyngier <marc.zyngier@arm.com>
MIME-Version 1.0
Content-Type text/plain; charset=us-ascii
Content-Disposition inline
User-Agent Mutt/1.5.23 (2014-03-12)
Sender robomod@news.nic.it
List-ID <linux-kernel.vger.kernel.org>
X-Mailing-List linux-kernel@vger.kernel.org
Approved robomod@news.nic.it
Lines 44
Organization linux.* mail to news gateway
X-Original-Cc Thomas Gleixner <tglx@linutronix.de>, Jason Cooper <jason@lakedaemon.net>, Will Deacon <will.deacon@arm.com>, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org
X-Original-Date Thu, 8 Oct 2015 16:56:55 +0100
X-Original-Message-ID <20151008155655.GO17192@e104818-lin.cambridge.arm.com>
X-Original-References <1443803874-9566-1-git-send-email-marc.zyngier@arm.com>
X-Original-Sender linux-kernel-owner@vger.kernel.org
Xref csiph.com linux.kernel:1242559

Show key headers only | View raw


On Fri, Oct 02, 2015 at 05:37:49PM +0100, Marc Zyngier wrote:
> Recent evolutions of the ARM Trusted Firmware have outlined issues
> when the system is equipped with a GICv3 interrupt controller, but the
> firmware has decided to restrict it to GICv2 compatibility mode.
> 
> In this mode, system registers cannot be enabled, and the firmware is
> expected to pass a GICv2 description (DT or ACPI tables).
> 
> This series makes sure that system register access is checked at EL2
> setup time and when the feature detection is performed. Additionally,
> the GICv2 driver checks that system registers are disabled, and warns
> if they are enabled.
> 
> The booting requirements are also updated to make the above explicit.
> 
> Marc Zyngier (5):
>   arm64: el2_setup: Make sure ICC_SRE_EL2.SRE sticks before using GICv3
>     sysregs
>   irqchip/gic-v3: Make gic_enable_sre an inline function
>   arm64: cpufeatures: Check ICC_EL1_SRE.SRE before enabling
>     ARM64_HAS_SYSREG_GIC_CPUIF
>   irqchip/gic: Warn if GICv3 system registers are enabled
>   arm64: Update booting requirements for GICv3 in GICv2 mode
> 
>  Documentation/arm64/booting.txt    | 11 ++++++++++-
>  arch/arm64/kernel/cpufeature.c     | 19 ++++++++++++++++++-
>  arch/arm64/kernel/head.S           |  2 ++
>  drivers/irqchip/irq-gic-v3.c       | 32 +++++++++-----------------------
>  drivers/irqchip/irq-gic.c          | 15 +++++++++++++++
>  include/linux/irqchip/arm-gic-v3.h | 16 ++++++++++++++++
>  6 files changed, 70 insertions(+), 25 deletions(-)

Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>

How do you plan to merge these patches? I'm fine for them to go via the
irqchip maintainers since they are all GIC related.

-- 
Catalin
--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Back to linux.kernel | Previous | NextNext in thread | Find similar | Unroll thread


Thread

Re: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode Catalin Marinas <catalin.marinas@arm.com> - 2015-10-08 18:00 +0200
  Re: [PATCH 0/5] arm64: Allow booting with GICv3 in GICv2 mode Marc Zyngier <marc.zyngier@arm.com> - 2015-10-08 18:10 +0200

csiph-web