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Re: [PATCH 01/25] x86, fpu: add placeholder for Processor Trace XSAVE state

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On Mon, 28 Sep 2015, Dave Hansen wrote:
> From: Dave Hansen <dave.hansen@linux.intel.com>
> 
> There is an XSAVE state component for Intel Processor Trace.  But,
> we do not use it and do not expect to ever use it.
> 
> We add a placeholder in the code for it so it is not a mystery and
> also so we do not need an explicit enum initialization for Protection
> Keys in a moment.
> 
> Why will we never use it?  According to Andi Kleen:
> 
> 	The XSAVE support assumes that there is a single buffer
> 	for each thread. But perf generally doesn't work this
> 	way, it usually has only a single perf event per CPU per
> 	user, and when tracing multiple threads on that CPU it
> 	inherits perf event buffers between different threads. So
> 	XSAVE per thread cannot handle this inheritance case
> 	directly.
> 
> 	Using multiple XSAVE areas (another one per perf event)
> 	would defeat some of the state caching that the CPUs do.
> 
> Signed-off-by: Dave Hansen <dave.hansen@linux.intel.com>

Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
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[PATCH 01/25] x86, fpu: add placeholder for Processor Trace XSAVE state Dave Hansen <dave@sr71.net> - 2015-09-28 21:30 +0200
  Re: [PATCH 01/25] x86, fpu: add placeholder for Processor Trace  XSAVE state Thomas Gleixner <tglx@linutronix.de> - 2015-10-01 13:10 +0200

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