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[PATCH 3/3] irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC

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gic_handle_shared_int reads the GIC interrupt pending & mask registers
directly into a bitmap, which is defined as an array of unsigned longs.
The GIC pending registers may be 32 bits wide if the CM is older than
CM3, regardless of the bit width of the CPU, but for MIPS64 kernels
the unsigned longs in the bitmap will be 64 bits wide. In this case we
need to perform 2 x 32 bit reads per 64 bit unsigned long in order to
avoid missing interrupts.

Signed-off-by: Paul Burton <paul.burton@imgtec.com>
---

 drivers/irqchip/irq-mips-gic.c | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/drivers/irqchip/irq-mips-gic.c b/drivers/irqchip/irq-mips-gic.c
index 842a53d..aeaa061 100644
--- a/drivers/irqchip/irq-mips-gic.c
+++ b/drivers/irqchip/irq-mips-gic.c
@@ -320,6 +320,14 @@ static void gic_handle_shared_int(bool chained)
 		intrmask[i] = gic_read(intrmask_reg);
 		pending_reg += gic_reg_step;
 		intrmask_reg += gic_reg_step;
+
+		if (!config_enabled(CONFIG_64BIT) || mips_cm_is64)
+			continue;
+
+		pending[i] |= (u64)gic_read(pending_reg) << 32;
+		intrmask[i] |= (u64)gic_read(intrmask_reg) << 32;
+		pending_reg += gic_reg_step;
+		intrmask_reg += gic_reg_step;
 	}
 
 	bitmap_and(pending, pending, intrmask, gic_shared_intrs);
-- 
2.5.3

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Thread

[PATCH 0/3] MIPS GIC fixes Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:30 +0200
  [PATCH 1/3] MIPS: CM: provide a function to map from CPU to VP ID Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:30 +0200
  [PATCH 2/3] irqchip: mips-gic: convert CPU numbers to VP IDs Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:40 +0200
  [PATCH 3/3] irqchip: mips-gic: fix pending & mask reads for MIPS64 with 32b GIC Paul Burton <paul.burton@imgtec.com> - 2015-09-22 20:40 +0200
  Re: [PATCH 0/3] MIPS GIC fixes Thomas Gleixner <tglx@linutronix.de> - 2015-09-22 21:10 +0200
    Re: [PATCH 0/3] MIPS GIC fixes Paul Burton <paul.burton@imgtec.com> - 2015-09-22 21:20 +0200
      Re: [PATCH 0/3] MIPS GIC fixes Thomas Gleixner <tglx@linutronix.de> - 2015-09-22 21:40 +0200

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