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Re: [PATCH v4] dmaengine: edma: fix residue race for cyclic

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On Thu, Jan 28, 2016 at 11:29:08AM +0100, John Ogness wrote:
> When retrieving the residue value, the SRC/DST fields of the
> active PaRAM are read to determine the current position of
> the DMA engine. However, the AM335x Technical Reference Manual
> states:
> 
>   11.3.3.6 Parameter Set Updates
> 
>   After the TR is read from the PaRAM (and is in the process
>   of being submitted to the EDMA3TC), the following fields are
>   updated as needed: ... SRC DST
> 
> This means SRC/DST is incremented even though the DMA transfer
> may not have started yet or is in progress. Thus if the reader
> of the residue accesses the DMA buffer too quickly, the CPU is
> misinformed about the data that has been successfully processed.
> 
> The CCSTAT.ACTV register is a boolean that is set if any TR is
> being processed by either the EMDA3CC or EDMA3TC. By polling
> this register it is possible to ensure that the residue value
> returned is valid for immediate processing. However, since the
> DMA engine may be active, polling may never hit a moment where
> no TR is being processed. To handle this, the SRC/DST is also
> polled to see if it changes. And as a last resort, a max loop
> count for the busy waiting exists to avoid an infinite loop.

Applied, thanks

-- 
~Vinod

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[PATCH v4] dmaengine: edma: fix residue race for cyclic John Ogness <john.ogness@linutronix.de> - 2016-01-28 11:30 +0100
  Re: [PATCH v4] dmaengine: edma: fix residue race for cyclic Peter Ujfalusi <peter.ujfalusi@ti.com> - 2016-02-01 15:00 +0100
  Re: [PATCH v4] dmaengine: edma: fix residue race for cyclic Vinod Koul <vinod.koul@intel.com> - 2016-02-08 04:20 +0100
  Re: [PATCH v4] dmaengine: edma: fix residue race for cyclic Andy Shevchenko <andy.shevchenko@gmail.com> - 2016-02-08 16:30 +0100

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