[PATCH] powerpc/885: set SDCR to 0x40

From	Christophe Leroy <christophe.leroy@c-s.fr>
Newsgroups	linux.kernel
Subject	[PATCH] powerpc/885: set SDCR to 0x40
Date	2016-02-04 11:20 +0100
Message-ID	<qYpb5-7ep-31@gated-at.bofh.it> (permalink)
Organization	linux.* mail to news gateway

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The MPC885 reference manual says that SDCR shall have value 0x40, but
most exemples set SDCR to 0x1
With 0x1 in SDCR, we observe TX underruns on SCC when using it in
QMC mode.
According the NXP technical support, this is a copy/paste error from
MPC860 reference manual, 0x40 being the only value supported
by the MPC885 HW.

Signed-off-by: Christophe Leroy <christophe.leroy@c-s.fr>
---
 arch/powerpc/sysdev/cpm1.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/powerpc/sysdev/cpm1.c b/arch/powerpc/sysdev/cpm1.c
index 5e6ff38..8ed6536 100644
--- a/arch/powerpc/sysdev/cpm1.c
+++ b/arch/powerpc/sysdev/cpm1.c
@@ -228,7 +228,10 @@ void __init cpm_reset(void)
 	 * Bit 25, FAM can also be set to use FEC aggressive mode (860T).
 	 */
 	siu_conf = immr_map(im_siu_conf);
-	out_be32(&siu_conf->sc_sdcr, 1);
+	if ((mfspr(SPRN_IMMR) & 0xffff) == 0x0900) /* MPC885 */
+		out_be32(&siu_conf->sc_sdcr, 0x40);
+	else
+		out_be32(&siu_conf->sc_sdcr, 1);
 	immr_unmap(siu_conf);
 
 	cpm_muram_init();
-- 
2.1.0

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[PATCH] powerpc/885: set SDCR to 0x40 Christophe Leroy <christophe.leroy@c-s.fr> - 2016-02-04 11:20 +0100

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