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Groups > linux.kernel > #1325823
| From | Mathieu Poirier <mathieu.poirier@linaro.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH V9 11/18] coresight: etm3x: consolidating initial config |
| Date | 2016-02-03 19:50 +0100 |
| Message-ID | <qYaF4-5Ec-9@gated-at.bofh.it> (permalink) |
| References | <qYavo-5AG-7@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
There is really no point in having two functions to take care
of doing the initial tracer configuration. As such moving
everything to 'etm_set_default()'.
Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++-----------------
1 file changed, 14 insertions(+), 23 deletions(-)
diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index 92139674bea4..34a69583ccbc 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO);
/* The number of ETM/PTM currently registered */
static int etm_count;
static struct etm_drvdata *etmdrvdata[NR_CPUS];
-static void etm_init_default_data(struct etm_config *config);
/*
* Memory mapped writes to clear os lock are not supported on some processors
@@ -194,6 +193,19 @@ void etm_set_default(struct etm_config *config)
if (WARN_ON_ONCE(!config))
return;
+ /*
+ * Taken verbatim from the TRM:
+ *
+ * To trace all memory:
+ * set bit [24] in register 0x009, the ETMTECR1, to 1
+ * set all other bits in register 0x009, the ETMTECR1, to 0
+ * set all bits in register 0x007, the ETMTECR2, to 0
+ * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
+ */
+ config->enable_ctrl1 = BIT(24);
+ config->enable_ctrl2 = 0x0;
+ config->enable_event = ETM_HARD_WIRE_RES_A;
+
config->trigger_event = ETM_DEFAULT_EVENT_VAL;
config->enable_event = ETM_HARD_WIRE_RES_A;
@@ -577,27 +589,6 @@ static void etm_init_arch_data(void *info)
CS_LOCK(drvdata->base);
}
-static void etm_init_default_data(struct etm_config *config)
-{
- if (WARN_ON_ONCE(!config))
- return;
-
- etm_set_default(config);
-
- /*
- * Taken verbatim from the TRM:
- *
- * To trace all memory:
- * set bit [24] in register 0x009, the ETMTECR1, to 1
- * set all other bits in register 0x009, the ETMTECR1, to 0
- * set all bits in register 0x007, the ETMTECR2, to 0
- * set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
- */
- config->enable_ctrl1 = BIT(24);
- config->enable_ctrl2 = 0x0;
- config->enable_event = ETM_HARD_WIRE_RES_A;
-}
-
static void etm_init_trace_id(struct etm_drvdata *drvdata)
{
/*
@@ -674,7 +665,7 @@ static int etm_probe(struct amba_device *adev, const struct amba_id *id)
}
etm_init_trace_id(drvdata);
- etm_init_default_data(&drvdata->config);
+ etm_set_default(&drvdata->config);
desc->type = CORESIGHT_DEV_TYPE_SOURCE;
desc->subtype.source_subtype = CORESIGHT_DEV_SUBTYPE_SOURCE_PROC;
--
2.1.4
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[PATCH V9 00/18] Coresight integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:40 +0100 [PATCH V9 11/18] coresight: etm3x: consolidating initial config Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 13/18] coresight: etm3x: implementing perf_enable/disable() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 14/18] coresight: etb10: moving to local atomic operations Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 18/18] coresight: introducing a global trace ID function Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 16/18] coresight: etb10: implementing AUX API Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 06/18] coresight: etm3x: unlocking tracers in default arch init Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 10/18] coresight: etm3x: changing default trace configuration Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 17/18] coresight: etm-perf: new PMU driver for ETM tracers Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 08/18] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 12/18] coresight: etm3x: implementing user/kernel mode tracing Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 15/18] coresight: etb10: adding operation mode for sink->enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 19:50 +0100 [PATCH V9 09/18] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 20:00 +0100 [PATCH V9 03/18] coresight: moving PM runtime operations to core framework Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 20:00 +0100 [PATCH V9 04/18] coresight: etm3x: moving etm_readl/writel to header file Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 20:00 +0100 [PATCH V9 02/18] coresight: add API to get sink from path Mathieu Poirier <mathieu.poirier@linaro.org> - 2016-02-03 20:00 +0100
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