Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy()

From	Tony Luck <tony.luck@gmail.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy()
Date	2016-01-30 01:40 +0100
Message-ID	<qWrK2-2Ro-9@gated-at.bofh.it> (permalink)
References	(6 earlier) <qPdiO-5Bj-3@gated-at.bofh.it> <qPmm6-3uu-9@gated-at.bofh.it> <qPIcX-17S-33@gated-at.bofh.it> <qQD1v-6Mu-1@gated-at.bofh.it> <qQI1b-1LZ-5@gated-at.bofh.it>
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On Wed, Jan 13, 2016 at 8:39 PM, Borislav Petkov <bp@alien8.de> wrote:
> On Wed, Jan 13, 2016 at 03:22:58PM -0800, Tony Luck wrote:
>> Are there some examples of synthetic CPUID bits?
>
> X86_FEATURE_ALWAYS is one. The others got renamed into X86_BUG_* ones,
> the remaining mechanism is the same, though.

So something like this [gmail will line wrap, but should still be legible]

Then Dan will be able to use:

      if (cpu_has(c, X86_FEATURE_MCRECOVERY))

to decide whether to use the (slightly slower, but recovery capable)
__mcsafe_copy()
or just pick the fastest memcpy() instead.

-Tony


diff --git a/arch/x86/include/asm/cpufeature.h
b/arch/x86/include/asm/cpufeature.h
index 7ad8c9464297..621e05103633 100644
--- a/arch/x86/include/asm/cpufeature.h
+++ b/arch/x86/include/asm/cpufeature.h
@@ -106,6 +106,7 @@
 #define X86_FEATURE_APERFMPERF ( 3*32+28) /* APERFMPERF */
 #define X86_FEATURE_EAGER_FPU  ( 3*32+29) /* "eagerfpu" Non lazy FPU restore */
 #define X86_FEATURE_NONSTOP_TSC_S3 ( 3*32+30) /* TSC doesn't stop in
S3 state */
+#define X86_FEATURE_MCRECOVERY ( 3*32+31) /* cpu has recoverable
machine checks */

 /* Intel-defined CPU features, CPUID level 0x00000001 (ecx), word 4 */
 #define X86_FEATURE_XMM3       ( 4*32+ 0) /* "pni" SSE-3 */
diff --git a/arch/x86/kernel/cpu/mcheck/mce.c b/arch/x86/kernel/cpu/mcheck/mce.c
index a006f4cd792b..b8980d767240 100644
--- a/arch/x86/kernel/cpu/mcheck/mce.c
+++ b/arch/x86/kernel/cpu/mcheck/mce.c
@@ -1694,6 +1694,14 @@ void mcheck_cpu_init(struct cpuinfo_x86 *c)
                return;
        }

+       /*
+        * MCG_CAP.MCG_SER_P is necessary but not sufficient to know
+        * whether this processor will actually generate recoverable
+        * machine checks. Check to see if this is an E7 model Xeon.
+        */
+       if (mca_cfg.ser && !strncmp(c->x86_model_id, "Intel(R) Xeon(R)
CPU E7-", 24))
+               set_cpu_cap(c, X86_FEATURE_MCRECOVERY);
+
        if (mce_gen_pool_init()) {
                mca_cfg.disabled = true;
                pr_emerg("Couldn't allocate MCE records pool!\n");

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Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy() Tony Luck <tony.luck@gmail.com> - 2016-01-30 01:40 +0100
  Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy() Borislav Petkov <bp@alien8.de> - 2016-01-30 11:30 +0100
    Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy() Tony Luck <tony.luck@gmail.com> - 2016-02-02 00:20 +0100
      Re: [PATCH v8 3/3] x86, mce: Add __mcsafe_copy() Dan Williams <dan.j.williams@intel.com> - 2016-02-02 00:20 +0100

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