Re: [PATCH] ASoC: wm8974: configure pll and mclk divider automatically

From	Charles Keepax <ckeepax@opensource.wolfsonmicro.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH] ASoC: wm8974: configure pll and mclk divider automatically
Date	2016-01-25 15:00 +0100
Message-ID	<qUPQt-4Ie-3@gated-at.bofh.it> (permalink)
References	<qUOB4-3Tm-25@gated-at.bofh.it>
Organization	linux.* mail to news gateway

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On Mon, Jan 25, 2016 at 12:36:43PM +0000, Mans Rullgard wrote:
> This adds a set_sysclk() DAI op so the card driver can set the
> input clock frequency.  If this is done, the pll and mclk divider
> are configured to produce the required 256x fs clock when the
> sample rate is set by hw_params().
> 
> These additions make the codec work with the simple-card driver.
> Card drivers calling set_pll() and set_clkdiv() directly are
> unaffected.
> 
> Signed-off-by: Mans Rullgard <mans@mansr.com>
> ---

Acked-by: Charles Keepax <ckeepax@opensource.wolfsonmicro.com>

Thanks,
Charles

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[PATCH] ASoC: wm8974: configure pll and mclk divider automatically Mans Rullgard <mans@mansr.com> - 2016-01-25 13:40 +0100
  Re: [PATCH] ASoC: wm8974: configure pll and mclk divider  automatically Charles Keepax <ckeepax@opensource.wolfsonmicro.com> - 2016-01-25 15:00 +0100

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