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Groups > linux.kernel > #1294652
| From | Peter Zijlstra <peterz@infradead.org> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions |
| Date | 2015-12-18 11:50 +0100 |
| Message-ID | <qH0LM-4tM-9@gated-at.bofh.it> (permalink) |
| References | <qGKQG-2xR-5@gated-at.bofh.it> <qGL0n-2Bm-27@gated-at.bofh.it> <qGLMK-3bD-21@gated-at.bofh.it> <qH0sq-4lf-27@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
On Fri, Dec 18, 2015 at 10:28:23AM +0000, Suzuki K. Poulose wrote:
> On 17/12/15 18:42, Peter Zijlstra wrote:
> >The above doesn't look like it has a failure case, in which case you can
> >achieve the same simpler, using pmu::pmu_{dis,en}able().
> >
>
> I thought about that, but was not sure if pmu->stop() is guaranteed to be
> called on all the events scheduled on the PMU when we pmu::pmu_disable().
> Is it ?
Not by core code, but you get to implement your pmu::pmu_disable() call,
and if that's what you need, you can make it do that.
Examples:
On some x86 hardware we indeed have to poke at each counter control
register and clear the ENable bit, which is the same what
pmu::stop(.flags=0) would do.
But other x86 hardware has a global disable switch, which is much
cheaper than poking at the individual counter control registers one by
one. In this case we only update the counter control register if it
needs updates (typically in the pmu_enable path).
Yet other x86 hardware can auto disable this global state on interrupt,
which saves us yet another machine register poke.
--
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[PATCHv4 00/12] arm-cci: PMU updates "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 18:50 +0100
[PATCH v4 09/12] arm-cci: Provide hook for writing to PMU counters "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 18:50 +0100
[PATCH v4 08/12] arm-cci: Add routines to save/restore all counters "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 18:50 +0100
[PATCH v4 11/12] arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 18:50 +0100
[PATCH v4 10/12] arm-cci: CCI-500: Work around PMU counter writes "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 02/12] arm-cci: Refactor pmu_write_counter "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 01/12] arm-cci: Define CCI counter period "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 06/12] arm-cci: Refactor CCI PMU enable/disable methods "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 05/12] arm-cci: PMU: Add support for transactions "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions Peter Zijlstra <peterz@infradead.org> - 2015-12-17 19:50 +0100
Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-12-18 11:30 +0100
Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions Peter Zijlstra <peterz@infradead.org> - 2015-12-18 11:50 +0100
Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions "Suzuki K. Poulose" <Suzuki.Poulose@arm.com> - 2015-12-18 12:00 +0100
Re: [PATCH v4 05/12] arm-cci: PMU: Add support for transactions Peter Zijlstra <peterz@infradead.org> - 2015-12-18 12:50 +0100
[PATCH v4 07/12] arm-cci: Get the status of a counter "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 03/12] arm-cci: Group writes to counter "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 04/12] arm-cci: Fix the flags for pmu_start called from pmu_add "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
[PATCH v4 12/12] arm-cci: CoreLink CCI-550 PMU driver "Suzuki K. Poulose" <suzuki.poulose@arm.com> - 2015-12-17 19:00 +0100
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