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Groups > linux.kernel > #1288965
| From | Rhyland Klein <rklein@nvidia.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config |
| Date | 2015-12-10 23:10 +0100 |
| Message-ID | <qEhzs-3G4-29@gated-at.bofh.it> (permalink) |
| References | <qEhzr-3G4-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
From: Mark Kuo <mkuo@nvidia.com> Fix PLLE spread spectrum configuration so it aligns with downstream kernel. Signed-off-by: Mark Kuo <mkuo@nvidia.com> Signed-off-by: Rhyland Klein <rklein@nvidia.com> --- drivers/clk/tegra/clk-pll.c | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-) diff --git a/drivers/clk/tegra/clk-pll.c b/drivers/clk/tegra/clk-pll.c index d9c3109b75bd..6ac3f843e7ca 100644 --- a/drivers/clk/tegra/clk-pll.c +++ b/drivers/clk/tegra/clk-pll.c @@ -86,15 +86,21 @@ #define PLLE_SS_DISABLE (PLLE_SS_CNTL_BYPASS_SS | PLLE_SS_CNTL_INTERP_RESET |\ PLLE_SS_CNTL_SSC_BYP) #define PLLE_SS_MAX_MASK 0x1ff -#define PLLE_SS_MAX_VAL 0x25 +#define PLLE_SS_MAX_VAL_TEGRA114 0x25 +#define PLLE_SS_MAX_VAL_TEGRA210 0x21 #define PLLE_SS_INC_MASK (0xff << 16) #define PLLE_SS_INC_VAL (0x1 << 16) #define PLLE_SS_INCINTRV_MASK (0x3f << 24) -#define PLLE_SS_INCINTRV_VAL (0x20 << 24) +#define PLLE_SS_INCINTRV_VAL_TEGRA114 (0x20 << 24) +#define PLLE_SS_INCINTRV_VAL_TEGRA210 (0x23 << 24) #define PLLE_SS_COEFFICIENTS_MASK \ (PLLE_SS_MAX_MASK | PLLE_SS_INC_MASK | PLLE_SS_INCINTRV_MASK) -#define PLLE_SS_COEFFICIENTS_VAL \ - (PLLE_SS_MAX_VAL | PLLE_SS_INC_VAL | PLLE_SS_INCINTRV_VAL) +#define PLLE_SS_COEFFICIENTS_VAL_TEGRA114 \ + (PLLE_SS_MAX_VAL_TEGRA114 | PLLE_SS_INC_VAL |\ + PLLE_SS_INCINTRV_VAL_TEGRA114) +#define PLLE_SS_COEFFICIENTS_VAL_TEGRA210 \ + (PLLE_SS_MAX_VAL_TEGRA210 | PLLE_SS_INC_VAL |\ + PLLE_SS_INCINTRV_VAL_TEGRA210) #define PLLE_AUX_PLLP_SEL BIT(2) #define PLLE_AUX_USE_LOCKDET BIT(3) @@ -1401,7 +1407,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val |= PLLE_MISC_IDDQ_SW_CTRL; val &= ~PLLE_MISC_IDDQ_SW_VALUE; val |= PLLE_MISC_PLLE_PTS; - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); pll_writel_misc(val, pll); udelay(5); @@ -1428,7 +1434,7 @@ static int clk_plle_tegra114_enable(struct clk_hw *hw) val = pll_readl(PLLE_SS_CTRL, pll); val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); val &= ~PLLE_SS_COEFFICIENTS_MASK; - val |= PLLE_SS_COEFFICIENTS_VAL; + val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA114; pll_writel(val, PLLE_SS_CTRL, pll); val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); pll_writel(val, PLLE_SS_CTRL, pll); @@ -2035,7 +2041,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) val |= PLLE_MISC_IDDQ_SW_CTRL; val &= ~PLLE_MISC_IDDQ_SW_VALUE; val |= PLLE_MISC_PLLE_PTS; - val |= PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK; + val &= ~(PLLE_MISC_VREG_BG_CTRL_MASK | PLLE_MISC_VREG_CTRL_MASK); pll_writel_misc(val, pll); udelay(5); @@ -2065,7 +2071,7 @@ static int clk_plle_tegra210_enable(struct clk_hw *hw) val = pll_readl(PLLE_SS_CTRL, pll); val &= ~(PLLE_SS_CNTL_CENTER | PLLE_SS_CNTL_INVERT); val &= ~PLLE_SS_COEFFICIENTS_MASK; - val |= PLLE_SS_COEFFICIENTS_VAL; + val |= PLLE_SS_COEFFICIENTS_VAL_TEGRA210; pll_writel(val, PLLE_SS_CTRL, pll); val &= ~(PLLE_SS_CNTL_SSC_BYP | PLLE_SS_CNTL_BYPASS_SS); pll_writel(val, PLLE_SS_CTRL, pll); -- 1.9.1 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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[PATCH 0/9] Tegra CLK Fixes Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:10 +0100 [PATCH 6/9] clk: tegra210: fix pllx dyn step calculation Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:10 +0100 [PATCH 8/9] clk: tegra: pll: Fix PLLE SS config Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:10 +0100 [PATCH 9/9] clk: tegra210: Initialize PLL_D2 to a sane rate Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:10 +0100 [PATCH 7/9] clk: tegra: pll: Do not disable PLLE when under HW control Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100 [PATCH 1/9] clk: tegra: Fix divider on VI_I2C Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100 [PATCH 4/9] clk: tegra: Fix the misnaming of nvenc from msenc Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100 [PATCH 5/9] clk: tegra: pll: Fix potential sleeping-while-atomic Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100 [PATCH 2/9] clk: tegra210: Remove improper flags for lock_enable Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100 [PATCH 3/9] clk: tegra210: Fix naming of MISC registers Rhyland Klein <rklein@nvidia.com> - 2015-12-10 23:20 +0100
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