Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller

From	Bjorn Helgaas <helgaas@kernel.org>
Newsgroups	linux.kernel
Subject	Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL PCIe Host Controller
Date	2015-12-10 18:30 +0100
Message-ID	<qEdcv-Km-17@gated-at.bofh.it> (permalink)
References	<qA8XL-5Zy-3@gated-at.bofh.it> <qDWbE-6rH-25@gated-at.bofh.it> <qE3wu-2QB-5@gated-at.bofh.it>
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On Thu, Dec 10, 2015 at 08:02:05AM +0100, Michal Simek wrote:
> Hi Bjorn,
> 
> On 10.12.2015 00:19, Bjorn Helgaas wrote:
> > [+cc Michal, Paul, Thierry, Stephen, Alexandre (see irq_dispose_mapping questions below)]
> > 
> > On Sun, Nov 29, 2015 at 05:33:53PM +0530, Bharat Kumar Gogada wrote:
> >> Adding PCIe Root Port driver for Xilinx PCIe NWL bridge IP.
> >>
> >> Signed-off-by: Bharat Kumar Gogada <bharatku@xilinx.com>
> >> Signed-off-by: Ravi Kiran Gummaluri <rgummal@xilinx.com>
> >> Acked-by: Rob Herring <robh@kernel.org>
> > 
> > This needs either a MAINTAINERS update or an ack from Michal (whose
> > MAINTAINERS entry matches anything containing "xilinx").
> 
> We have done it in this way because driver owners are changing time to
> time and my entry cover it that I can pass it to appropriate person who
> is responsible for it.
> 
> For this Maintainers part here is my:
> Acked-by: Michal Simek <michal.simek@xilinx.com>

Thanks.

For things under drivers/pci/host, I ask for an ack from the
individual maintainer before applying patches.  As-is (without a
MAINTAINERS update) I'll be looking for acks from you, Michal, for all
future changes to pcie-xilinx-nwl.c.  If you want something else, we
need a MAINTAINERS change.

Bjorn
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Thread

Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Michal Simek <michal.simek@xilinx.com> - 2015-12-10 08:10 +0100
  Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Bjorn Helgaas <helgaas@kernel.org> - 2015-12-10 18:30 +0100
    Re: [PATCH v11] PCI: Xilinx-NWL-PCIe: Added support for Xilinx NWL  PCIe Host Controller Michal Simek <michal.simek@xilinx.com> - 2015-12-11 08:40 +0100

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