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Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d posted-interrupts

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2015-12-09 08:19+0000, Wu, Feng:
>> -----Original Message-----
>> From: Radim Krčmář [mailto:rkrcmar@redhat.com]
>> Sent: Tuesday, November 17, 2015 3:03 AM
>> To: Wu, Feng <feng.wu@intel.com>
>> Cc: pbonzini@redhat.com; kvm@vger.kernel.org; linux-kernel@vger.kernel.org
>> Subject: Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d posted-
>> interrupts
>> 
>> 2015-11-09 10:46+0800, Feng Wu:
>> > +struct kvm_vcpu *kvm_intr_vector_hashing_dest(struct kvm *kvm,
>> > +					      struct kvm_lapic_irq *irq)
>> > +
>> > +{
>> > +	unsigned long dest_vcpu_bitmap[BITS_TO_LONGS(KVM_MAX_VCPUS)];
>> > +	unsigned int dest_vcpus = 0;
>> > +	struct kvm_vcpu *vcpu;
>> > +	unsigned int i, mod, idx = 0;
>> > +
>> > +	vcpu = kvm_intr_vector_hashing_dest_fast(kvm, irq);
>> > +	if (vcpu)
>> > +		return vcpu;
>> 
>> I think the rest of this function shouldn't be implemented:
>>  - Shorthands are only for IPIs and hence don't need to be handled,
>>  - Lowest priority physical broadcast is not supported,
>>  - Lowest priority cluster logical broadcast is not supported,
>>  - No point in optimizing mixed xAPIC and x2APIC mode,
> 
> I read your comments again, and don't quite understand why we
> don't need PI optimization for mixed xAPIC and x2APIC mode.

There shouldn't be a non-hobbyist operating system that uses mixed mode,
so the optimization would practically be dead code as all other cases
are handled by kvm_intr_vector_hashing_dest_fast().

I think that having extra code would bring problems in the future -- we
need to take care of it when refactoring KVM's APIC and we should also
write a unit-test for this otherwise dead path.  I don't think that the
benefit for guests would ever balance those efforts.

(Physical xAPIC+x2APIC mode is still somewhat reasonable and xAPIC CPUs
 start with LDR=0, which means that operating system doesn't need to
 utilize mixed mode, as defined by KVM, when switching to x2APIC.)

> BTW, can we have mixed flat and cluster mode?

Yes, KVM recognizes that mixed mode, but luckily, there are severe
limitations.

Notes below SDM section 10.6.2.2:
  All processors that have their APIC software enabled (using the
  spurious vector enable/disable bit) must have their DFRs (Destination
  Format Registers) programmed identically.

I hope there isn't a human that would use it in good faith.

(Only NMI/SMI/INIT/SIPI are delivered in software disabled mode and if
 the system uses cluster xAPIC, OS should set DFR before LDR, which
 doesn't trigger mixed mode either.)
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RE: [PATCH] KVM: x86: Add lowest-priority support for vt-d  posted-interrupts "Wu, Feng" <feng.wu@intel.com> - 2015-12-09 09:30 +0100
  Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d  posted-interrupts Radim Krčmář <rkrcmar@redhat.com> - 2015-12-09 16:00 +0100
    RE: [PATCH] KVM: x86: Add lowest-priority support for vt-d  posted-interrupts "Wu, Feng" <feng.wu@intel.com> - 2015-12-10 03:00 +0100
      Re: [PATCH] KVM: x86: Add lowest-priority support for vt-d  posted-interrupts Radim Krcmár <rkrcmar@redhat.com> - 2015-12-11 15:40 +0100

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