Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > linux.kernel > #1284592

[PATCH v5 02/11] spi: imx: reorder HW operations enable order to avoid possible RX data loss

Show all headers | View raw

The overflow may happen due to rescheduling for another task and/or interrupt
if we enable SPI HW before starting RX DMA. So RX DMA enabled first to make
sure data would be read out from FIFO ASAP. TX DMA enabled next to start
filling TX FIFO with new data. And finaly SPI HW enabled to start actual
data transfer.

The risk rise in case of heavy system load and high SPI clock.

Signed-off-by: Anton Bondarenko <anton.bondarenko.sama@gmail.com>
---
 drivers/spi/spi-imx.c | 12 ++++++++++--
 1 file changed, 10 insertions(+), 2 deletions(-)

diff --git a/drivers/spi/spi-imx.c b/drivers/spi/spi-imx.c
index fb3bcc4..17e8f9e 100644
--- a/drivers/spi/spi-imx.c
+++ b/drivers/spi/spi-imx.c
@@ -946,10 +946,18 @@ static int spi_imx_dma_transfer(struct spi_imx_data *spi_imx,
 	if (left)
 		writel(dma | (left << MX51_ECSPI_DMA_RXT_WML_OFFSET),
 				spi_imx->base + MX51_ECSPI_DMA);
+	/*
+	 * Set these order to avoid potential RX overflow. The overflow may
+	 * happen if we enable SPI HW before starting RX DMA due to rescheduling
+	 * for another task and/or interrupt.
+	 * So RX DMA enabled first to make sure data would be read out from FIFO
+	 * ASAP. TX DMA enabled next to start filling TX FIFO with new data.
+	 * And finaly SPI HW enabled to start actual data transfer.
+	 */
+	dma_async_issue_pending(master->dma_rx);
+	dma_async_issue_pending(master->dma_tx);
 	spi_imx->devtype_data->trigger(spi_imx);
 
-	dma_async_issue_pending(master->dma_tx);
-	dma_async_issue_pending(master->dma_rx);
 	/* Wait SDMA to finish the data transfer.*/
 	timeout = wait_for_completion_timeout(&spi_imx->dma_tx_completion,
 						IMX_DMA_TIMEOUT);
-- 
2.6.3

--
To unsubscribe from this list: send the line "unsubscribe linux-kernel" in
the body of a message to majordomo@vger.kernel.org
More majordomo info at  http://vger.kernel.org/majordomo-info.html
Please read the FAQ at  http://www.tux.org/lkml/

Back to linux.kernel | Previous | Next — Previous in thread | Next in thread | Find similar | Unroll thread

Thread

[PATCH v5 00/11] Improvements for SPI IMX driver for Freescale IMX51, IMX53 and IMX6 Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
  [PATCH v5 06/11] spi: imx: return error from dma channel request Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
    Re: [PATCH v5 06/11] spi: imx: return error from dma channel request Sascha Hauer <s.hauer@pengutronix.de> - 2015-12-07 10:40 +0100
      Re: [PATCH v5 06/11] spi: imx: return error from dma channel request Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-08 00:40 +0100
  [PATCH v5 01/11] spi: imx: terminate RX DMA transaction in case of TX DMA timeout Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
  [PATCH v5 08/11] spi: imx: allow only WML aligned transfers to use DMA Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
    Re: [PATCH v5 08/11] spi: imx: allow only WML aligned transfers to  use DMA Sascha Hauer <s.hauer@pengutronix.de> - 2015-12-07 10:50 +0100
      Re: [PATCH v5 08/11] spi: imx: allow only WML aligned transfers to  use DMA Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-08 01:40 +0100
        Re: [PATCH v5 08/11] spi: imx: allow only WML aligned transfers to  use DMA Sascha Hauer <s.hauer@pengutronix.de> - 2015-12-08 07:10 +0100
  [PATCH v5 07/11] spi: imx: defer spi initialization, if DMA engine is Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
  [PATCH v5 02/11] spi: imx: reorder HW operations enable order to avoid possible RX data loss Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100
  [PATCH v5 10/11] spi: imx: replace fixed timeout with calculated Anton Bondarenko <anton.bondarenko.sama@gmail.com> - 2015-12-05 18:00 +0100

csiph-web