Re: [PATCH resend 1/6] clk: sunxi: Add DRAM gates support for sun4i-a10

From	Maxime Ripard <maxime.ripard@free-electrons.com>
Newsgroups	linux.kernel
Subject	Re: [PATCH resend 1/6] clk: sunxi: Add DRAM gates support for sun4i-a10
Date	2015-12-07 10:00 +0100
Message-ID	<qCZOi-2cf-19@gated-at.bofh.it> (permalink)
References	<qCkUN-1wZ-7@gated-at.bofh.it> <qCkUN-1wZ-9@gated-at.bofh.it>
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On Sat, Dec 05, 2015 at 09:16:42PM +0800, Chen-Yu Tsai wrote:
> The A10/A20 share the same set of DRAM clock gates, which controls
> direct memory access for some peripherals.
> 
> On the A10, bit 15 controls the system's DRAM clock output (possibly
> to the DRAM chips), which we need to keep on.
> 
> On the A20 this has been moved to the DRAM controller, becoming a no-op.
> However it is still listed in the user manual, so add it anyway.
> 
> Signed-off-by: Chen-Yu Tsai <wens@csie.org>

Applied, thanks!
Maxime

-- 
Maxime Ripard, Free Electrons
Embedded Linux, Kernel and Android engineering
http://free-electrons.com

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[PATCH resend 1/6] clk: sunxi: Add DRAM gates support for sun4i-a10 Chen-Yu Tsai <wens@csie.org> - 2015-12-05 14:20 +0100
  Re: [PATCH resend 1/6] clk: sunxi: Add DRAM gates support for  sun4i-a10 Maxime Ripard <maxime.ripard@free-electrons.com> - 2015-12-07 10:00 +0100

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