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RE: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips

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>From: Marc Zyngier [mailto:marc.zyngier@arm.com] 
>Sent: Tuesday, December 01, 2015 3:29 PM

> +  interrupt source. The value shall be 1.

>So you never have to encode the interrupt trigger type? Do you only support edge or level?
I Always use level sensitive.

> +
> +#define NPS_GIM_P_EN	0x100	/* Peripheral interrupts source enable */
> +#define NPS_GIM_P_BLK	0x118	/* Peripheral interrupts blocking for sources */

>>Are these the interrupts the peripherals are using? If yes, they really have nothing to do here...
I will move this from here 
>> +	__asm__ __volatile__ (
>> +	"       .word %0\n"
>> +	:
>> +	: "i"(CTOP_INST_RSPI_GIC_0_R12)
>> +	: "memory");

>Silly question: why cannot you just write the actual instruction instead of shoving the instruction like this? Also, .inst would be more appropriate...
[Noam Camus] Since this is instruction that yet is not part of up-streamed binutils of ARC.  Now ARC maintainer can build our kernel with generic ARC toolchain. 

>> +static int nps400_irq_map(struct irq_domain *d, unsigned int irq,
>> +			  irq_hw_number_t hw)
>> +{
>> +	switch (irq) {
>> +	case TIMER0_IRQ:
>> +#if defined(CONFIG_SMP)
>> +	case IPI_IRQ:
>> +#endif
>> +		irq_set_chip_and_handler(irq, &nps400_irq_chip_percpu,
>> +					 handle_percpu_irq);
>> +	break;
>> +	default:
>> +		irq_set_chip_and_handler(irq, &nps400_irq_chip_fasteoi,
>> +					 handle_fasteoi_irq);
>> +	break;
>> +	}

>No. This is just wrong. Either you get per interrupt information from the device tree to configure the interrupt the right way, or you have different interrupt controllers for each device.
I am not sure how you want me to get it from DTB? Please refer to some reference.

>But using the Linux irq number is always wrong. You should only consider the hwirq.
I will change

> +
> +	nps400_root_domain = irq_domain_add_legacy(node, NR_CPU_IRQS, 0, 0,
> +						   &nps400_irq_ops, NULL);

>And that's why you can get away with the above horror. Don't use legacy domains. This stuff is by no mean legacy.
So what is my alternative here?

-Noam
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[PATCH v3 00/18] *** SUBJECT HERE *** Noam Camus <noamc@ezchip.com> - 2015-12-01 14:10 +0100
  Re: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips Marc Zyngier <marc.zyngier@arm.com> - 2015-12-01 14:30 +0100
    RE: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips Noam Camus <noamc@ezchip.com> - 2015-12-02 16:10 +0100
      Re: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips Marc Zyngier <marc.zyngier@arm.com> - 2015-12-03 19:40 +0100
        RE: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips Noam Camus <noamc@ezchip.com> - 2015-12-07 12:20 +0100
    Re: [PATCH v3 04/18] irqchip: add nps Internal and external irqchips Vineet Gupta <Vineet.Gupta1@synopsys.com> - 2015-12-11 09:00 +0100
  Re: [PATCH v3 01/18] Documentation: Add EZchip vendor to binding list Daniel Lezcano <daniel.lezcano@linaro.org> - 2015-12-04 09:10 +0100
    Re: [PATCH v3 01/18] Documentation: Add EZchip vendor to binding list Noam Camus <noamc@ezchip.com> - 2015-12-04 12:50 +0100
  Re: [PATCH v3 03/18] clocksource: Add NPS400 timers driver Daniel Lezcano <daniel.lezcano@linaro.org> - 2015-12-04 10:20 +0100
    Re: [PATCH v3 03/18] clocksource: Add NPS400 timers driver Noam Camus <noamc@ezchip.com> - 2015-12-04 13:30 +0100
      Re: [PATCH v3 03/18] clocksource: Add NPS400 timers driver Daniel Lezcano <daniel.lezcano@linaro.org> - 2015-12-04 14:00 +0100
    RE: [PATCH v3 03/18] clocksource: Add NPS400 timers driver Noam Camus <noamc@ezchip.com> - 2015-12-08 14:10 +0100

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