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Groups > linux.kernel > #1279525

[PATCH V5 12/26] coresight: etm3x: consolidating initial config

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There is really no point in having two functions to take care
of doing the initials tracer configuration.  As such moving
everything to 'etm_set_default()'.

Signed-off-by: Mathieu Poirier <mathieu.poirier@linaro.org>
---
 drivers/hwtracing/coresight/coresight-etm3x.c | 37 ++++++++++-----------------
 1 file changed, 14 insertions(+), 23 deletions(-)

diff --git a/drivers/hwtracing/coresight/coresight-etm3x.c b/drivers/hwtracing/coresight/coresight-etm3x.c
index cfaf8e840bd6..14927da0f6ba 100644
--- a/drivers/hwtracing/coresight/coresight-etm3x.c
+++ b/drivers/hwtracing/coresight/coresight-etm3x.c
@@ -41,7 +41,6 @@ module_param_named(boot_enable, boot_enable, int, S_IRUGO);
 /* The number of ETM/PTM currently registered */
 static int etm_count;
 static struct etm_drvdata *etmdrvdata[NR_CPUS];
-static void etm_init_default_data(struct etm_config *config);
 
 /*
  * Memory mapped writes to clear os lock are not supported on some processors
@@ -199,7 +198,7 @@ struct etm_config *get_etm_config(struct etm_drvdata *drvdata)
 		return NULL;
 
 	/* Set default config */
-	etm_init_default_data(config);
+	etm_set_default(config);
 	drvdata->config = config;
 out:
 	return drvdata->config;
@@ -212,6 +211,19 @@ void etm_set_default(struct etm_config *config)
 	if (WARN_ON_ONCE(!config))
 		return;
 
+	/*
+	 * Taken verbatim from the TRM:
+	 *
+	 * To trace all memory:
+	 *  set bit [24] in register 0x009, the ETMTECR1, to 1
+	 *  set all other bits in register 0x009, the ETMTECR1, to 0
+	 *  set all bits in register 0x007, the ETMTECR2, to 0
+	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
+	 */
+	config->enable_ctrl1 = BIT(24);
+	config->enable_ctrl2 = 0x0;
+	config->enable_event = ETM_HARD_WIRE_RES_A;
+
 	config->trigger_event = ETM_DEFAULT_EVENT_VAL;
 	config->enable_event = ETM_HARD_WIRE_RES_A;
 
@@ -606,27 +618,6 @@ static void etm_init_arch_data(void *info)
 	CS_LOCK(drvdata->base);
 }
 
-static void etm_init_default_data(struct etm_config *config)
-{
-	if (WARN_ON_ONCE(!config))
-		return;
-
-	etm_set_default(config);
-
-	/*
-	 * Taken verbatim from the TRM:
-	 *
-	 * To trace all memory:
-	 *  set bit [24] in register 0x009, the ETMTECR1, to 1
-	 *  set all other bits in register 0x009, the ETMTECR1, to 0
-	 *  set all bits in register 0x007, the ETMTECR2, to 0
-	 *  set register 0x008, the ETMTEEVR, to 0x6F (TRUE).
-	 */
-	config->enable_ctrl1 = BIT(24);
-	config->enable_ctrl2 = 0x0;
-	config->enable_event = ETM_HARD_WIRE_RES_A;
-}
-
 static void etm_init_trace_id(struct etm_drvdata *drvdata)
 {
 	/*
-- 
2.1.4

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[PATCH V5 00/26] Coresight integration with perf  Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 08/26] coresight: etm3x: adding operation mode for etm_enable() Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 22/26] coresight: introducing a global trace ID function Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 07/26] coresight: moving PM runtime operations to core framework Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 23/26] perf tools: making function set_max_cpu_num() non static Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 10/26] coresight: etm3x: set progbit to stop trace collection Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 18/26] coresight: etb10: implementing AUX space API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:20 +0100
  [PATCH V5 19/26] coresight: updating documentation to reflect integration with perf Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100
  [PATCH V5 12/26] coresight: etm3x: consolidating initial config Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100
  [PATCH V5 14/26] coresight: etm3x: adding perf_get/set_config() API Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100
  [PATCH V5 16/26] coresight: etb10: moving to local atomic operations Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100
  [PATCH V5 09/26] coresight: add API to get sink from path Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100
  [PATCH V5 11/26] coresight: etm3x: changing default trace configuration Mathieu Poirier <mathieu.poirier@linaro.org> - 2015-11-30 03:30 +0100

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