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Groups > linux.kernel > #1159820
| From | Hans Ulli Kroll <ulli.kroll@googlemail.com> |
|---|---|
| Newsgroups | linux.kernel |
| Subject | [PATCH 3/6] ARM:Gemini:add missing intr state and mask register |
| Date | 2015-06-06 06:00 +0200 |
| Message-ID | <pydr3-4Z4-1@gated-at.bofh.it> (permalink) |
| References | <pydr3-4Z4-3@gated-at.bofh.it> |
| Organization | linux.* mail to news gateway |
For earch timer function we have intr state and mask register. Add control bits up/down counting for each timer Signed-off-by: Hans Ulli Kroll <ulli.kroll@googlemail.com> --- arch/arm/mach-gemini/time.c | 17 +++++++++++++++++ 1 file changed, 17 insertions(+) diff --git a/arch/arm/mach-gemini/time.c b/arch/arm/mach-gemini/time.c index 76e3ca7..a8604a3 100644 --- a/arch/arm/mach-gemini/time.c +++ b/arch/arm/mach-gemini/time.c @@ -28,6 +28,8 @@ #define TIMER_MATCH1(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x08) #define TIMER_MATCH2(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x0C) #define TIMER_CR(BASE_ADDR) (IO_ADDRESS(BASE_ADDR) + 0x30) +#define TIMER_INTR_STATE (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x34) +#define TIMER_INTR_MASK (IO_ADDRESS(GEMINI_TIMER_BASE) + 0x38) #define TIMER_1_CR_ENABLE (1 << 0) #define TIMER_1_CR_CLOCK (1 << 1) @@ -38,6 +40,21 @@ #define TIMER_3_CR_ENABLE (1 << 6) #define TIMER_3_CR_CLOCK (1 << 7) #define TIMER_3_CR_INT (1 << 8) +#define TIMER_1_CR_UPDOWN (1 << 9) +#define TIMER_2_CR_UPDOWN (1 << 10) +#define TIMER_3_CR_UPDOWN (1 << 11) + +#define TIMER_1_INT_MATCH1 (1 << 0) +#define TIMER_1_INT_MATCH2 (1 << 1) +#define TIMER_1_INT_OVERFLOW (1 << 2) +#define TIMER_2_INT_MATCH1 (1 << 3) +#define TIMER_2_INT_MATCH2 (1 << 4) +#define TIMER_2_INT_OVERFLOW (1 << 5) +#define TIMER_3_INT_MATCH1 (1 << 6) +#define TIMER_3_INT_MATCH2 (1 << 7) +#define TIMER_3_INT_OVERFLOW (1 << 8) +#define TIMER_INT_ALL_MASK 0x1ff + static unsigned int tick_rate; -- 2.4.2 -- To unsubscribe from this list: send the line "unsubscribe linux-kernel" in the body of a message to majordomo@vger.kernel.org More majordomo info at http://vger.kernel.org/majordomo-info.html Please read the FAQ at http://www.tux.org/lkml/
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[PATCH 3/6] ARM:Gemini:add missing intr state and mask register Hans Ulli Kroll <ulli.kroll@googlemail.com> - 2015-06-06 06:00 +0200
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