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Re: [PATCH V7 3/5] arm64: mm: add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT

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+Cc Ard and Leif.

On 07/22/2015 05:59 AM, Jonathan (Zhixiong) Zhang wrote:
> From: "Jonathan (Zhixiong) Zhang" <zjzhang@codeaurora.org>
>
> UEFI spec 2.5 section 2.3.6.1 defines that EFI_MEMORY_[UC|WC|WT|WB] are
> possible EFI memory types for AArch64. Each of those EFI memory types
> is mapped to a corresponding AArch64 memory type. So we need to define
> PROT_DEVICE_nGnRnE and PROT_NORMWL_WT.
>
> MT_NORMAL_WT is defined, and its encoding is added to MAIR_EL1 when
> initializing cpu.
>
> Change-Id: I20ac71ddf74c17e41769ecbb5f8c60eeefbb398a
> Signed-off-by: Jonathan (Zhixiong) Zhang <zjzhang@codeaurora.org>
> ---
>   arch/arm64/include/asm/memory.h  | 1 +
>   arch/arm64/include/asm/pgtable.h | 2 ++
>   arch/arm64/mm/proc.S             | 6 ++++--
>   3 files changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/arm64/include/asm/memory.h b/arch/arm64/include/asm/memory.h
> index f800d45ea226..4112b3d7468e 100644
> --- a/arch/arm64/include/asm/memory.h
> +++ b/arch/arm64/include/asm/memory.h
> @@ -100,6 +100,7 @@
>   #define MT_DEVICE_GRE		2
>   #define MT_NORMAL_NC		3
>   #define MT_NORMAL		4
> +#define MT_NORMAL_WT		5
>
>   /*
>    * Memory types for Stage-2 translation
> diff --git a/arch/arm64/include/asm/pgtable.h b/arch/arm64/include/asm/pgtable.h
> index 800ec0e87ed9..5c108ad13558 100644
> --- a/arch/arm64/include/asm/pgtable.h
> +++ b/arch/arm64/include/asm/pgtable.h
> @@ -61,8 +61,10 @@ extern void __pgd_error(const char *file, int line, unsigned long val);
>   #define PROT_SECT_DEFAULT	(PMD_TYPE_SECT | PMD_SECT_AF)
>   #endif
>
> +#define PROT_DEVICE_nGnRnE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRnE))
>   #define PROT_DEVICE_nGnRE	(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_DEVICE_nGnRE))
>   #define PROT_NORMAL_NC		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_NC))
> +#define PROT_NORMAL_WT		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL_WT))
>   #define PROT_NORMAL		(PROT_DEFAULT | PTE_PXN | PTE_UXN | PTE_ATTRINDX(MT_NORMAL))
>
>   #define PROT_SECT_DEVICE_nGnRE	(PROT_SECT_DEFAULT | PMD_SECT_PXN | PMD_SECT_UXN | PMD_ATTRINDX(MT_DEVICE_nGnRE))
> diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S
> index 838266f5b056..23e265d732f8 100644
> --- a/arch/arm64/mm/proc.S
> +++ b/arch/arm64/mm/proc.S
> @@ -294,7 +294,7 @@ ENTRY(__cpu_setup)
>   	msr	cpacr_el1, x0			// Enable FP/ASIMD
>   	msr	mdscr_el1, xzr			// Reset mdscr_el1
>   	/*
> -	 * Memory region attributes for LPAE:
> +	 * Memory region attributes for LPAE and EFI:
>   	 *
>   	 *   n = AttrIndx[2:0]
>   	 *			n	MAIR
> @@ -303,12 +303,14 @@ ENTRY(__cpu_setup)
>   	 *   DEVICE_GRE		010	00001100
>   	 *   NORMAL_NC		011	01000100
>   	 *   NORMAL		100	11111111
> +	 *   NORMAL_WT		101	10111011
>   	 */
>   	ldr	x5, =MAIR(0x00, MT_DEVICE_nGnRnE) | \
>   		     MAIR(0x04, MT_DEVICE_nGnRE) | \
>   		     MAIR(0x0c, MT_DEVICE_GRE) | \
>   		     MAIR(0x44, MT_NORMAL_NC) | \
> -		     MAIR(0xff, MT_NORMAL)
> +		     MAIR(0xff, MT_NORMAL) | \
> +		     MAIR(0xbb, MT_NORMAL_WT)
>   	msr	mair_el1, x5
>   	/*
>   	 * Prepare SCTLR
>
--
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Re: [PATCH V7 3/5] arm64: mm: add PROT_DEVICE_nGnRnE and PROT_NORMAL_WT Hanjun Guo <hanjun.guo@linaro.org> - 2015-07-24 05:00 +0200

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