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Re: [RFC PATCH] mtd: spi-nor: Added flag check for quad io protocol for micron flash parts

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Hi, I don't really have enough knowledge to comment QUAD IO, I'll just
include some general comments.

On 18 June 2015 at 16:58, Anurag Kumar Vulisha
<anurag.kumar.vulisha@xilinx.com> wrote:
> micron flash parts by default operates in extended spi protocol,which accepts
> command on single line and can accept address & data on one,two and four lines
> depending on the command sent.In set_quad_enable() we are enabling the quad io
> protocol for micron flash parts by updating the EVCR register,in this method the
> flash expects the command,address and data to be transmitted on all four data
> lines which may not be supported on all qspi controllers.So READ_1_1_4 command
> does not necessarily go out using those bus widths.
>
> So i have added SPI_QUAD_IO_PROTOCOL flag,which should be checked before enabling
> the quad io protocol.

Above description is a bit of pain to read & understand. Long
sentences, lacking spaces after interpunction signs, small letters in
"micron", "spi" etc., lines over 72 chars. You really could do better
:)


> @@ -55,6 +55,7 @@ struct flash_info {
>  #define        SPI_NOR_DUAL_READ       0x20    /* Flash supports Dual Read */
>  #define        SPI_NOR_QUAD_READ       0x40    /* Flash supports Quad Read */
>  #define        USE_FSR                 0x80    /* use flag status register */
> +#define SPI_QUAD_IO_PROTOCOL   0x100   /* use quad io protocol */

All defines use tab so follow this way (don't use space instead).
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Re: [RFC PATCH] mtd: spi-nor: Added flag check for quad io protocol  for micron flash parts Rafał Miłecki <zajec5@gmail.com> - 2015-06-20 21:20 +0200

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