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Phantom reads on 6502, 65C02 and 65816

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  Phantom reads on 6502, 65C02 and 65816 ol.sc@web.de (Oliver Schmidt) - 2020-05-06 17:04 +0000
    Re: Phantom reads on 6502, 65C02 and 65816 Andy McFadden <thefadden@gmail.com> - 2020-05-06 17:20 -0700
      Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-06 21:15 -0700
        Re: Phantom reads on 6502, 65C02 and 65816 Antoine Vignau <ntn.vignau@gmail.com> - 2020-05-06 23:29 -0700
          Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-07 01:20 -0700
        Re: Phantom reads on 6502, 65C02 and 65816 ol.sc@web.de (Oliver Schmidt) - 2020-05-07 09:33 +0000
          Re: Phantom reads on 6502, 65C02 and 65816 TomCh <tomcharlesworth26@gmail.com> - 2020-05-07 04:48 -0700
            Re: Phantom reads on 6502, 65C02 and 65816 ol.sc@web.de (Oliver Schmidt) - 2020-05-07 12:33 +0000
              Re: Phantom reads on 6502, 65C02 and 65816 kegs@provalid.com (Kent Dickey) - 2020-05-07 09:23 -0500
                Re: Phantom reads on 6502, 65C02 and 65816 Andy McFadden <thefadden@gmail.com> - 2020-05-07 10:02 -0700
                  Re: Phantom reads on 6502, 65C02 and 65816 Andy McFadden <thefadden@gmail.com> - 2020-05-07 11:27 -0700
                    Re: Phantom reads on 6502, 65C02 and 65816 Antoine Vignau <ntn.vignau@gmail.com> - 2020-05-07 12:25 -0700
                    Re: Phantom reads on 6502, 65C02 and 65816 Andy McFadden <thefadden@gmail.com> - 2020-05-16 19:05 -0700
                      Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-18 06:09 -0700
                        Re: Phantom reads on 6502, 65C02 and 65816 Andy McFadden <thefadden@gmail.com> - 2020-05-26 07:42 -0700
                          Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-27 00:04 -0700
                  Re: Phantom reads on 6502, 65C02 and 65816 Anthony Lawther <alawther@spammenot.mac.com> - 2020-05-09 07:54 +0900
                Re: Phantom reads on 6502, 65C02 and 65816 ol.sc@web.de (Oliver Schmidt) - 2020-05-07 19:28 +0000
                Re: Phantom reads on 6502, 65C02 and 65816 kegs@provalid.com (Kent Dickey) - 2020-05-07 15:16 -0500
                  Re: Phantom reads on 6502, 65C02 and 65816 Antoine Vignau <ntn.vignau@gmail.com> - 2020-05-07 15:07 -0700
                    Re: Phantom reads on 6502, 65C02 and 65816 kegs@provalid.com (Kent Dickey) - 2020-05-07 19:48 -0500
                      Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-07 18:46 -0700
          Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-07 08:32 -0700
            Re: Phantom reads on 6502, 65C02 and 65816 ol.sc@web.de (Oliver Schmidt) - 2020-05-07 19:36 +0000
            Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-07 23:39 -0700
              Re: Phantom reads on 6502, 65C02 and 65816 Antoine Vignau <ntn.vignau@gmail.com> - 2020-05-08 01:20 -0700
                Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-08 01:41 -0700
              Re: Phantom reads on 6502, 65C02 and 65816 Nick Westgate <nick.westgate@gmail.com> - 2020-05-08 05:46 -0700

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#5554

In article <7017df26-8397-4605-9d2f-47ab0b7332ec@googlegroups.com>,
Antoine Vignau  <ntn.vignau@gmail.com> wrote:
>To Kent,
>answer to the false read in disk code is explained on page 2, paragraph
>3 of
>http://www.brutaldeluxe.fr/documentation/iwm/iwm_discussion_19820531.pdf
>
>It would be great to find Apple Computer's 6502 false read cycles
>document, mentioned on page 3 of the same document
>
>Antoine

Great information!

From that document:

"3) The IWM does not require the false-read cycle, which occurs on indexed
write instructions such as STA $C05E,X, to work properly.  The Disk Controller
state machine depends on the false read cycle during the STA Q7H,X instruction
to store data properly into the shift register.  This anamoly means that
software which may work with the IWM will not work with the Disk Controller.
This type of problem will generally appear if a store absolute instruction is
used to set Q7H (STA $C0EF), since there is no false-read cycle on store
absolute operations."

This is what I was guessing was the problem, but it's explicitly explained.
The problem would likely affect the code which re-wrote sector data since
the timing is critical there.

It also implies that the Apple IIc, with the IWM, has a 65c02 without
the false-reads.

Kent

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#5555

On Friday, 8 May 2020 10:48:13 UTC+10, Kent Dickey  wrote:
> Great information!

Indeed, thanks for all the great docs, Antoine.

> It also implies that the Apple IIc, with the IWM, has a 65c02 without
> the false-reads.

I don't think this is the case, but I'll try to test it later today.
As Tom said, this is well documented by Sather (as I posted above).
If true then a //e enhancement kit would fail with RWTS.

The terminology is confusing. There are invalid and multiple accesses.
The 65C02 removes all (?) invalid (reads) and some multiple accesses.

STA (zp),Y became a single write, which fixes the POKE problem.
But STA abs,X still has the read then write, to work with RWTS.
The cycle count is the same - for the same reason.

Here's what Sather said on page 4-26:
"From this induced idle state,
the software can syne itself to the logic sequencer
with the statement, "STA $C08F,X". This instruction
performs a double access to $COEF (assuming
Slot 6). The first access is decoded in the disk controller
to cause the logic state sequencer to leave its
idle state and begin its write loop. The second access
stores actual disk write data in the controller's input/
output register. The controller will only accept data
on the clockpulse after the one which started the
logic state sequencer and on every fourth clockpulse
afterward. The writing technique involves writing
data in software loops that take exact multiples of
four cycles to execute.

Persons wishing to imitate the writing technique
of the RWTS subroutine should not substitute a
"STA $COEF" instruction for the "STA $C08F,X" at
address $B83F of DOS 3.3, "STA $COEF" will start
up the software loop one clockpulse out of sync with
the logic state sequencer, and the controller won't
accept the write data. "STA $COEF,X" will work
with 0 in the X-register. The instruction must make
a double access to $COEF."

What's surprising is that he missed some things though...
On page 4-25 he wrote:
"* Statements marked by an asterisk in this application note are
true for the 6502 but not the 65C02."

But at the end of the previous quote from 4-26
"Another address mode of
instruction which will work is a STA (ZP),Y with no
page crossing."

This should have an asterisk if his 65C02 changes are correct.
It won't work on a 65C02.

Cheers,
Nick.

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#5546

On Thursday, 7 May 2020 19:33:30 UTC+10, Oliver Schmidt  wrote:
> But now you seem to agree with Andy that STA abs,x "doesn't touch
> memory twice". I guess you understand that this leaves me pretty
> puzzled.

Yeah, it's confusing: it depends on which STA (etc) instruction. In the NMOS 6502 instructions there were some multiple (double etc) accesses, and there were some invalid accesses (to the destination address - $100). The 65C02 got rid of all the invalid accesses, but only some of the multiple accesses. 

That's what I expressed surprise about in that thread - that POKE was still considered a double access (it's not on a 65C02) - but that some double accesses remained - of course they had to for the disk controller to work.

After that great summary from Kent, here's some data - I've heard conflicting things about the IIgs too, so I just tested it ... But first, for NMOS 6502 vs 65C02 I mostly trust Sather:

Understanding the Apple //e - tables on pages 4-23 & 4-27
X-REG = 20
70/71 CONTAIN 5772 OR 57F2 AS NEEDED FOR ILLUSTRATION

NMOS 6502
20 LDA 5772,X NX 1000=BD l00l=72 1002=57 5792=DATA
21 LDA 57F2,X PX 1000=BD l00l=F2 1002=57 5712=IGNORE 5812=DATA
21 STA 57F2,X PX 1000=BD l00l=F2 1002=57 5712=IGNORE 5812=DATAW
22 STA 5772,X NX 1000=9D l00l=72 1002=57 5792=IGNORE 5792=DATAW
...
28 STA (70),Y NX 1000=91 l00l=70 0070=72 0071=57 5792=IGNORE 5792=DATAW

65C02
20 LDA 5772,X NX 1000=BD l00l=72 1002=57 5792=DATA
21 LDA 57F2,X PX 1000=BD l00l=F2 1002=57 *1002=57 5812=DATA
21 STA 57F2,X PX 1000=BD l00l=F2 1002=57 *1002=57 5812=DATAW
22 STA 5772,X NX 1000=9D l00l=72 1002=57 5792=IGNORE 5792=DATAW
...
28 STA (70),Y NX 1000=91 l00l=70 0070=72 0071=57 *0071=57 5792=DATAW

* marks changed behaviour in the 65C02.
LDA/STA abs,X page crossing (PX) fixed invalid accesses.
STA abs,X no page crossing (NX) still has double accesses.
STA (zp),Y NX now has single accesses. This fixes POKE.

Now for the IIgs...
300: A2 51 BD FF C0 4C DA FD

LDX #51
LDA C0FF,X
JMP FDDA

I.e.
X-REG = 51
21 LDA C0FF,X PX 0300=BD 030l=FF 0302=C0 C050=IGNORE C150=DATA

This turns on graphics mode, so C050 was touched.
And it prints 22, which is the value of C150.

And it didn't matter if:
e=0/1
x=0/1
m=0/1
Change to LDY and LDA abs,Y

So it seems the 65C816 (in my ROM 3 IIgs) behaves a lot like an NMOS 6502.
The CPU is a CMD (micro symbol) G65SC816P-4 from 1989.

I also tested the above on a //e with an NCR 65C02A.
The graphics stayed off, so no invalid access.

The best test for STA (zp),Y is probably the Language Card switches, but that probably doesn't concern you so much, and it's late. ; - )

Cheers,
Nick.

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#5551

Hi Nick,

>[...]
>* marks changed behaviour in the 65C02.
>LDA/STA abs,X page crossing (PX) fixed invalid accesses.
>STA abs,X no page crossing (NX) still has double accesses.
>STA (zp),Y NX now has single accesses. This fixes POKE.

I see.

>[...]
>So it seems the 65C816 (in my ROM 3 IIgs) behaves a lot like an NMOS 6502.
>The CPU is a CMD (micro symbol) G65SC816P-4 from 1989.

I see.

>I also tested the above on a //e with an NCR 65C02A.
>The graphics stayed off, so no invalid access.

I see.

Thank you very much for the effort you put into the hands-on
verification!

Regards,
Oliver

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#5556

On Friday, 8 May 2020 01:32:51 UTC+10, Nick Westgate  wrote:
> The best test for STA (zp),Y is probably the Language Card switches, but that probably doesn't concern you so much, and it's late. ; - )

I had a spare few minutes and tested STA (zp),Y on the 65C02.
It would be good to test on the IIgs, but the IIgs monitor is a bit tricky.

Anyway, first we need to make sure we have an F8 ROM, eg:
C081 C081 N F800<F800.FFFFM

Now consider the following code at say 300:
 LDA #$C0
 STA $01
 LDA #$81
 STA $00
 LDA #$00
 TAX
 TAY
 BIT $C080
 BIT $C081
 BIT $C081 ;READ 2
 STA $D000
 BIT $C080
 RTS

This will set $D000 to 0 in LC RAM Bank 2.

The second read (BIT $C081) is necessary to enable LC RAM write.
If we change BIT to STA with 312:8D, the code fails to change $D000.

We can test STA abs,X with 312:9D. This works, so there is a read.
Now STA (zp),Y with 312:91 00 EA. This fails; there is no read.

Antoine's document suggests the 65816 will have a read too (page 5-18).
Perhaps someone who knows the IIgs Quagmire register well could have a go.

Cheers,
Nick.

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#5557

And the most passionating document is the cycle-by-cycle listing at http://www.brutaldeluxe.fr/documentation/cortland/v7%2065SC816%20opcodes%20Cycle%20by%20cycle%20listing.pdf

Chapter 5 lists all opcodes for a 65816 in full emulation mode.

Read it before going to bed :-)
Antoine

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#5558

On Friday, 8 May 2020 18:20:58 UTC+10, Antoine Vignau  wrote:
> And the most passionating document is the cycle-by-cycle listing at http://www.brutaldeluxe.fr/documentation/cortland/v7%2065SC816%20opcodes%20Cycle%20by%20cycle%20listing.pdf
> 
> Chapter 5 lists all opcodes for a 65816 in full emulation mode.
> 
> Read it before going to bed :-)
> Antoine

Yes, great resource, thanks so much.

I referred to it in my post above about STA (zp),Y:
"Antoine's document suggests the 65816 will have a read too (page 5-18)."

Testing this from the IIgs monitor is a bit tricky though.
Any tips for setting the language card? C080 etc don't work.

Cheers,
Nick.

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#5559

On Friday, 8 May 2020 16:39:59 UTC+10, Nick Westgate  wrote:
> Now STA (zp),Y with 312:91 00 EA. This fails; there is no read.

Confirmed STA (zp),Y on the IIgs, so there is a read as per Antoine's docs.

(The IIgs monitor is great fun for hacking around in assembly.)

Cheers,
Nick.

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