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More about race conditions and memory visibility

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  More about race conditions and memory visibility aminer68@gmail.com - 2019-08-04 14:23 -0700

#10118 — More about race conditions and memory visibility

Hello,



More about race conditions and memory visibility:


I said previously about the memory visibility problem the following:

===============================================================

I have come to an interesting subject about memory visibility..

As you know that in parallel programming you have to take care 
not only of memory ordering , but also take care about memory visibility, 
read this to notice it:


Store Barrier

A store barrier, “sfence” instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued.  This will make the program state "visible" to other CPUs so they can act on it if necessary.  

I think that this is also the case in ARM CPUs and other CPUs..

So as you are noticing that i think that this memory visibility problem is 
rendering parallel programming more "difficult" and more "dangerous".


What do you think about it ?

==============================================================



I think this memory visibility problem can give race conditions, 
so this is a problem because read this about race conditions:


NP-hard problem means there is no known algorithm can solve it in a polynomial time, so that the time to find a solution grows exponentially with problem size. Although it has not been definitively proven that, there is no polynomial algorithm for solving NP-hard problems, many eminent mathematicians have tried and failed.

Race condition detection is NP-hard

Read more here:

https://pages.mtu.edu/~shene/NSF-3/e-Book/RACE/difficult.html



Thank you,
Amine Moulay Ramdane.

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