More about memory visibility..

Newsgroups	comp.programming
Date	2019-08-14 16:52 -0700
Message-ID	<c6681636-fb4a-4a75-9c6e-bf0322dcbca0@googlegroups.com> (permalink)
Subject	More about memory visibility..
From	aminer68@gmail.com

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Hello,


More about memory visibility..

I said before:

As you know that in parallel programming you have to take care 
not only of memory ordering , but also take care about memory visibility, read this to notice it:

A store barrier, “sfence” instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued.  This will make the program state "visible" to other CPUs so they can act on it if necessary.  


Read more here to understand correctly:

"However under x86-TSO, the stores are cached in the store buffers,
a load consult only shared memory and the store buffer of the given thread, wich means it can load data from memory and ignore values from 
the other thread."

Read more here:

https://books.google.ca/books?id=C2R2DwAAQBAJ&pg=PA127&lpg=PA127&dq=immediately+visible+and+m+fence+and+store+buffer+and+x86&source=bl&ots=yfGI17x1YZ&sig=ACfU3U2EYRawTkQmi3s5wY-sM7IgowDlWg&hl=en&sa=X&ved=2ahUKEwi_nq3duYPkAhVDx1kKHYoyA5UQ6AEwAnoECAgQAQ#v=onepage&q=immediately%20visible%20and%20m%20fence%20and%20store%20buffer%20and%20x86&f=false



Thank you,
Amine Moulay Ramdane.

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More about memory visibility.. aminer68@gmail.com - 2019-08-14 16:52 -0700

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