Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.programming.threads > #5427 > unrolled thread

Here is another problem with ARM processors..

Back to article view | Back to comp.programming.threads

Contents

  Here is another problem with ARM processors.. aminer68@gmail.com - 2019-12-27 12:33 -0800
    Re: Here is another problem with ARM processors.. Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 12:49 +0100
      Re: Here is another problem with ARM processors.. aminer68@gmail.com - 2019-12-28 08:45 -0800
        Re: Here is another problem with ARM processors.. Bonita Montero <Bonita.Montero@gmail.com> - 2019-12-28 19:14 +0100

#5427 — Here is another problem with ARM processors..

Hello..


Here is another problem with ARM processors..


About SC and TSO and RMO hardware memory models..

I have just read the following webpage about the performance difference
between: SC and TSO and RMO hardware memory models

I think TSO is better, it is just around 3% ~ 6% less performance
than RMO and it is a simpler programming model than RMO. So i think ARM
must support TSO to be compatible with x86 that is TSO.

Read more here to notice it:

https://infoscience.epfl.ch/record/201695/files/CS471_proj_slides_Tao_Marc_2011_1222_1.pdf

About memory models and sequential consistency:

As you have noticed i am working with x86 architecture..

Even though x86 gives up on sequential consistency, it’s among the most
well-behaved architectures in terms of the crazy behaviors it allows.
Most other architectures implement even weaker memory models.

ARM memory model is notoriously underspecified, but is essentially a
form of weak ordering, which provides very few guarantees. Weak ordering
allows almost any operation to be reordered, which enables a variety of
hardware optimizations but is also a nightmare to program at the lowest
levels.

Read more here:

https://homes.cs.washington.edu/~bornholt/post/memory-models.html


Memory Models: x86 is TSO, TSO is Good

Essentially, the conclusion is that x86 in practice implements the old
SPARC TSO memory model.

The big take-away from the talk for me is that it confirms the
observation made may times before that SPARC TSO seems to be the optimal
memory model. It is sufficiently understandable that programmers can
write correct code without having barriers everywhere. It is
sufficiently weak that you can build fast hardware implementation that
can scale to big machines.

Read more here:

https://jakob.engbloms.se/archives/1435


Thank you,
Amine Moulay Ramdane.

[toc] | [next] | [standalone]

#5430

> I think TSO is better, it is just around 3% ~ 6% less performance

It's impossible to estimate that since you can't build a ARM-CPU
with TSO for comparison.

[toc] | [prev] | [next] | [standalone]

#5431

On Saturday, December 28, 2019 at 6:49:29 AM UTC-5, Bonita Montero wrote:
> > I think TSO is better, it is just around 3% ~ 6% less performance
> 
> It's impossible to estimate that since you can't build a ARM-CPU
> with TSO for comparison.



Read again, it says:

"ARM’s weak memory model could provide good performance.
But TSO could provide simpler programming model with 3% ~ 6% performance penalties."

Read more here to notice it:

https://infoscience.epfl.ch/record/201695/files/CS471_proj_slides_Tao_Marc_2011_1222_1.pdf


Thank you,
Amine Moulay Ramdane.

[toc] | [prev] | [next] | [standalone]

#5432

> Read again, it says:
> "ARM’s weak memory model could provide good performance.
> But TSO could provide simpler programming model with 3% ~ 6% performance penalties."

It's impossible to prove that.

[toc] | [prev] | [standalone]

Back to top | Article view | comp.programming.threads

csiph-web