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Read gain, i correct some last typos

Started byHorizon68 <horizon@horizon.com>
First post2019-01-30 12:44 -0800
Last post2019-01-30 12:44 -0800
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  Read gain, i correct some last typos Horizon68 <horizon@horizon.com> - 2019-01-30 12:44 -0800

#4913 — Read gain, i correct some last typos

FromHorizon68 <horizon@horizon.com>
Date2019-01-30 12:44 -0800
SubjectRead gain, i correct some last typos
Message-ID<q2t2c9$ju6$23@dont-email.me>
Hello,,


Read gain, i correct some last typos:

About some of my scalable algorithms..

As you have noticed, i am a white arab who has invented many scalable 
algorithms and there implementations, and two of my interesting scalable 
algorithms are the following:

LW_Asym_RWLockX that is a lightweight scalable Asymmetric Reader-Writer 
Mutex that uses a technic that looks like Seqlock without looping on the 
reader side like Seqlock, and this has permited the reader side to be 
costless, it is FIFO fair on the writer side and FIFO fair on the reader 
side and it is of course Starvation-free and it does spin-wait, and also 
Asym_RWLockX a lightweight scalable Asymmetric Reader-Writer Mutex that 
uses a technic that looks like Seqlock without looping on the reader 
side like Seqlock, and this has permited the reader side to be costless, 
it is FIFO fair on the writer side and FIFO fair on the reader side and 
it is of course Starvation-free and it does not spin-wait, but waits on 
my SemaMonitor, so it is energy efficient.

And i am using the Windows FlushProcessWriteBuffers for those two 
atomic-free “highly asymmetric synchronizations”, this greatly increase 
read-side speed and scalability.

You can download the C++ and Delphi and FreePascal implementations of my
scalable algorithms above from:

The C++ implementation is inside my C++ synchronization objects library 
here:

https://sites.google.com/site/scalable68/c-synchronization-objects-library

And the Delphi and FreePascal implementations are here:

https://sites.google.com/site/scalable68/scalable-rwlock


Here is also why my scalable algorithms above are useful:

Based on Intel and Micron's claim, 3D Xpoint is 1000x faster than NAND 
and 10x higher density than conventional memory (assume DRAM here). So 
latency of PCIe NAND is about 100us, and 1000x faster 3D Xpoint gives 
100ns, which is 2 times slower than DRAM's speed of 50ns, so this makes 
my scalable RWLocks very useful for 3D Xpoint, so my scalable RWLocks 
are for example very useful for Optane SSD 900P that uses 3D Xpoint and
thus they are very useful for such SSDs that use 3D XPoint and that are 
used in a "scalable" RAID manner.

Read about Intel Optane SSD 900P Review: 3D XPoint Unleashed

https://www.tomshardware.co.uk/intel-optane-ssd-900p-3d-xpoint,review-34076.html



Thank you,
Amine Moulay Ramdane.

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