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About memory models and sequential consistency

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  About memory models and sequential consistency Horizon68 <horizon@horizon.com> - 2018-12-19 11:53 -0800

#4801 — About memory models and sequential consistency

Hello...


About memory models and sequential consistency:

As you have noticed i am working with x86 architecture..

Even though x86 gives up on sequential consistency, it’s among the most 
well-behaved architectures in terms of the crazy behaviors it allows. 
Most other architectures implement even weaker memory models.

ARM memory model is notoriously underspecified, but is essentially a 
form of weak ordering, which provides very few guarantees. Weak ordering 
allows almost any operation to be reordered, which enables a variety of 
hardware optimizations but is also a nightmare to program at the lowest 
levels.

Read more here:

https://homes.cs.washington.edu/~bornholt/post/memory-models.html


Memory Models: x86 is TSO, TSO is Good

Essentially, the conclusion is that x86 in practice implements the old 
SPARC TSO memory model.

The big take-away from the talk for me is that it confirms the 
observation made may times before that SPARC TSO seems to be the optimal 
memory model. It is sufficiently understandable that programmers can 
write correct code without having barriers everywhere. It is 
sufficiently weak that you can build fast hardware implementation that 
can scale to big machines.

Read more here:

https://jakob.engbloms.se/archives/1435


Thank you,
Amine Moulay Ramdane.

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