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About my scalable algorithms and ARM processor architecture..

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Hello...


About my scalable algorithms and ARM processor architecture..

I have thought more, and i am specialized in parallel programming
and synchronization algorithms, and i have invented many scalable 
algorithms and there implementations, you will find some of them in my 
website here:

https://sites.google.com/site/scalable68/


My scalable algorithms and there implementations are actually compatible
with x86 architecture, but I have just taken a look at the following ARM 
processor, and even though it's not a TSO memory model, and even though 
it is a weak memory model, i think i am more capable to easily port my
scalable algorithms to such ARM processors, so i will easily port many 
of my "scalable" algorithms to such the following ARM processors, here
is how: i think i have to 64-byte align some of my variables
in my scalable algorithms implementations so that to be atomic or/and to 
avoid false sharing, also it is good that the ARM processors such as 
Cortex-A76 below have 64-byte cache lines and this cache line size of 
64-byte is compatible with x86, so it will easy for me the work of 
porting to ARM, and i will easily put the right fences for ARM in my 
scalable algorithms implementation so that to be compatible with such 
the following ARM processors and this step is easy
for me because i am more capable, now my scalable algorithms 
implementations are compatible with x86 architecture
and i will soon easily port them to ARM.

Here is the Cortex-A76 - Microarchitectures - ARM
notice that it has 64-byte cache lines as x86:


https://en.wikichip.org/wiki/arm_holdings/microarchitectures/cortex-a76


So stay tuned ! because i will soon easily port all my scalable 
algorithms to such ARM processors.




Thank you,
Amine Moulay Ramdane.

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About my scalable algorithms and ARM processor architecture.. Horizon68 <horizon@horizon.com> - 2019-03-06 13:25 -0800

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