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I have just taken a look at the Memory ordering of ARM CPU architecture

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Hello..


I have just taken a look at the Memory ordering of ARM CPU architecture 
here:

https://en.wikipedia.org/wiki/Memory_ordering

And i think that there is something happening with weak memory models 
like ARM and this is not good, take for example my scalable MLock
or my scalable AMLock that i have invented here:

https://sites.google.com/site/scalable68/scalable-mlock

and here:

https://sites.google.com/site/scalable68/scalable-amlock


They are working now with x86 memory model that is a
TSO memory model like Sparc TSO, but to be able to port them
to ARM i have to use more memory barrier that costs more
than on x86, also there is another problem is that
you can make more errors on the memory ordering process on the weaker 
memory model of ARM. So i think i will stay with x86 CPU architecture, 
and not port my scalable algorithms on ARM, because ARM must
provide us with a TSO memory model to be able to be more
efficient.


About memory models and sequential consistency:

As you have noticed i am working with x86 architecture..

Even though x86 gives up on sequential consistency, it’s among the most 
well-behaved architectures in terms of the crazy behaviors it allows. 
Most other architectures implement even weaker memory models.

ARM memory model is notoriously underspecified, but is essentially a 
form of weak ordering, which provides very few guarantees. Weak ordering 
allows almost any operation to be reordered, which enables a variety of 
hardware optimizations but is also a nightmare to program at the lowest 
levels.

Read more here:

https://homes.cs.washington.edu/~bornholt/post/memory-models.html


Memory Models: x86 is TSO, TSO is Good

Essentially, the conclusion is that x86 in practice implements the old 
SPARC TSO memory model.

The big take-away from the talk for me is that it confirms the 
observation made may times before that SPARC TSO seems to be the optimal 
memory model. It is sufficiently understandable that programmers can 
write correct code without having barriers everywhere. It is 
sufficiently weak that you can build fast hardware implementation that 
can scale to big machines.

Read more here:

https://jakob.engbloms.se/archives/1435


Thank you,
Amine Moulay Ramdane.

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I have just taken a look at the Memory ordering of ARM CPU architecture Horizon68 <horizon@horizon.com> - 2019-02-01 14:35 -0800

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