Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.programming.threads > #5481

About data races in parallel programming..

Show all headers | View raw

Hello,


About data races in parallel programming..

I have just read the following webpage:

Benign Data Races: What Could Possibly Go Wrong?

https://software.intel.com/en-us/blogs/2013/01/06/benign-data-races-what-could-possibly-go-wrong


And as you have noticed in the above webpage that you have to be careful with compilers in parallel programming so that to avoid data races, because compilers can optimize global variables if it is not volatile, and this can cause data races in parallel programming, i am understanding this issue, and i am for example using dynamic memory in Freepascal and Delphi for global variables that are written by the main thread and read by many other threads , also i know how to use memory fences to force visibility, and i also know around how how much time takes the store buffer to drain etc.

Read my following thoughts to undertand more:
 

About the store buffer and memory visibility..


More about memory visibility..

I said before:

As you know that in parallel programming you have to take care 
not only of memory ordering , but also take care about memory visibility, read this to notice it:

A store barrier, “sfence” instruction on x86, forces all store instructions prior to the barrier to happen before the barrier and have the store buffers flushed to cache for the CPU on which it is issued.  This will make the program state "visible" to other CPUs so they can act on it if necessary.  


Read more here to understand correctly:

"However under x86-TSO, the stores are cached in the store buffers,
a load consult only shared memory and the store buffer of the given thread, wich means it can load data from memory and ignore values from 
the other thread."

Read more here:

https://books.google.ca/books?id=C2R2DwAAQBAJ&pg=PA127&lpg=PA127&dq=immediately+visible+and+m+fence+and+store+buffer+and+x86&source=bl&ots=yfGI17x1YZ&sig=ACfU3U2EYRawTkQmi3s5wY-sM7IgowDlWg&hl=en&sa=X&ved=2ahUKEwi_nq3duYPkAhVDx1kKHYoyA5UQ6AEwAnoECAgQAQ#v=onepage&q=immediately%20visible%20and%20m%20fence%20and%20store%20buffer%20and%20x86&f=false


Now can we ask the question of how much time takes the 
store buffer to drain ?


So read here to notice:

https://nicknash.me/2018/04/07/speculating-about-store-buffer-capacity/


So as you are noticing he is giving around 500 no-ops to allow the store 
buffer to drain, and i think that it can take less than that for the store buffer to drain.



Thank you,
Amine Moulay Ramdane.

Back to comp.programming.threads | Previous | Next | Find similar | Unroll thread

Thread

About data races in parallel programming.. aminer68@gmail.com - 2020-01-16 15:04 -0800

csiph-web