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Call for papers: Dataflow Models for Extreme Scale Computing (DFM 2014)

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  Call for papers: Dataflow Models for Extreme Scale Computing (DFM 2014) Stéphane Zuckerman <szuckerm@udel.edu> - 2014-05-03 16:38 -0400

#1066 — Call for papers: Dataflow Models for Extreme Scale Computing (DFM 2014)

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	FORTH WORKSHOP ON DATA-FLOW EXECUTION MODELS
	FOR EXTREME SCALE COMPUTING (DFM 2014)

	to be held in conjunction with PACT 2014

	August 24, 2014, Edmonton, Alberta, Canada


Important Dates:
Submission Deadline:     June 16th
Notification of Authors: July 12th
Camera Ready:            July 20th

The Fourth International workshop on “Data-Flow Models (DFM) for 
extreme scale computing” will be held in conjunction with PACT 2014 in 
Edmonton, Alberta, Canada in August 2014.

The purpose of DFM continues being to bring together those researchers 
interested in novel computational models based on Data-Flow principles 
of execution. The switch to multi-core systems has raised concurrency to 
the level of a major issue if we are to use the increasing number of 
cores in a chip.

In the past five decades, sequential computing dominated the computer 
architecture landscape because designers were successful at building 
faster and faster computers by solely relying on improvements on 
fabrication technologies and architectural/organization optimizations. 
The most severe limitation of the sequential model, namely its inability 
to tolerate long memory latencies has slowed down the performance gains. 
This phenomenon is the ubiquitous Memory Wall. While various mechanisms 
have been implemented to overcome the wall (such as extremely efficient 
hardware prefetch support for example), they only add to another wall 
that hampers highly efficient execution of programs and modern chip 
design: the Power Wall. Power considerations and heat dissipation issues 
have forced manufacturers to switch to multiple cores per chip and thus 
move into the concurrency era.

New concurrent models/paradigms are needed in order to fully utilize the 
potential of Multi-core chips. The Data-flow model is a formal model 
that can handle concurrency and tolerate memory and synchronization 
latencies. Data-Flow inspired systems could also be simpler and more 
power efficient than conventional systems.

Recent work has shown that the Data-Flow principles can be used to 
develop systems that can outperform systems based on conventional 
techniques. Thus, it is time to revisit Data-driven computation and 
bring it to the Multi-core and extreme scale computing.

DFM 2014 solicits novel papers that include but are not limited to:
- Novel Data-Flow inspired Execution models and Architectures
- Functional and Single assignment based Languages.
- Strict and non-strict execution models.
- Compilers and tools for Data-Flow/Data-Driven systems.
- Hybrid Data-driven/Control-driven systems.
- Position Papers on the Future of Data-Flow in the Multi-core era and 
beyond.

DFM 2014 will accept both Full (8 pages) and Short papers (4 pages). 
Papers should be prepared using the IEEE Proceedings format, Submit your 
paper via the EASY CHAIR

All accepted papers will appear in the IEEE Xplore Digital Library. 
Extended versions of the best papers will be invited to submit for 
special issue of IJPP (International Journal on Parallel Programming).



STEERING Committee:
Skevos Evripidou , University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, Univ. of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo


PUBLICITY CHAIR:
Giorgos Matheou, University of Cyprus
Stéphane Zuckerman, Univ. of Delaware


PROGRAM COMMITTEE:
Skevos Evripidou, University of Cyprus
Guang Gao, University of Delaware
Jean-Luc Gaudiot, Univ. of California at Irvine
Vivek Sarkar, Rice University
Ian Watson, University of Manchester
Kei Hiraki, University of Tokyo
David Abramson, Monash University
Costas Kyriacou, Frederic University
Pedro Trancoso, University of Cyprus
Kyriacos Stavrou, Intel Labs Barcelona, SP
John Feo, Pacific Northwest National Laboratory
Bob Iannucci, CMU, Silicon Valley, USA
Wallid Najjar, University of California, Riverside
Wolfgang Karl,  KIT,  Germany
Mark Oskin, University of Washington
Andrew Sohn, NJIT, USA
Reiner Hartenstein, TU  Kaiserslautern
Kemal Ebcioğlu, Global Supercomputing Corp.
Kevin Hammond, University of St Andrews
Roberto Giorgi, University of Sienna
Robert Clay, Sandia National Labs
Sven-Bodo Scholz, Heriot-Watt University
Stéphane Zuckerman, Univ. of Delaware


PROCEEDING CHAIR:
Costas Kyriacou, Frederic University Cyprus


-- 
Stéphane Zuckerman
Computer Architecture & Parallel Systems Laboratories (CAPSL)
University of Delaware, 201G Evans Hall, Newark DE 19716
Work#: 302 831 6534 / Cell#: +1 302 883 9979

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