Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.parallel > #230 > unrolled thread

[ecsi-2] CfP Deadline March 23 > ESLsyn-Electronic System Level Synthesis Conference > June 2-3, San Francisco, CA

Back to article view | Back to comp.parallel

Contents

  [ecsi-2] CfP Deadline March 23 > ESLsyn-Electronic System Level Synthesis Conference > June 2-3, San Francisco, CA "info@ecsi.org" <info@ecsi.org> - 2012-03-18 14:56 +0000

#230 — [ecsi-2] CfP Deadline March 23 > ESLsyn-Electronic System Level Synthesis Conference > June 2-3, San Francisco, CA

[http://www.ecsi.org/sites/default/files/images/ESLsyn-small.jpg]<http://www
.ecsi.org/eslsyn>
Electronic System Level Synthesis Conference
June 2-3, 2012
San Francisco, California, USA
General Co-Chairs:
Sandeep K. Shukla, Virginia Tech, US & Philippe Coussy, Lab-STICC, FR
Program Co-Chairs:
Jens Brandt, TU Kaiserslautern, DE & Achim Rettberg, U. of Oldenburg, DE
Organization Chair: Adam Morawiec, ECSI, FR

www.ecsi.org/eslsyn

ESLsyn is organized with the technical co-sponsorship
the IEEE Council on Electronic Design Automation (CEDA)

 [http://www.ecsi.org/sites/default/files/images/IEEE.gif]
[http://www.ecsi.org/sites/default/files/images/CEDA_Logo_small2.jpg]

Description

The ever-increasing need for enhanced productivity in designing highly
complex electronic systems drives the evolution of design methods beyond the
traditional approaches. Virtual prototyping, design space exploration and
system synthesis with the goal of optimized and functionally correct product
implementations are needed for designing both HW and SW parts. ESL design
does not only provide system architects with the right tools to make the
right decisions about the system architecture, it includes the methodologies
and techniques that correlate the ESL model. A well-connected
ESL-to-implementation design flow is needed.

The system design teams expect newer and more efficient methods and tools
supporting better management of the design complexity and reduction of the
design cycle time all together, breaking the trend to compromise on the
evaluation of various design implementation options. Designing at higher
levels of abstraction is a viable way to better cope with the system design
complexity, to verify earlier in the design process and to increase code
reuse.

The Electronic System Level Synthesis Conference ESLsyn focuses on automated
system design methods that enable efficient modelling of systems to provide
the capability to synthesize HW platforms and embedded software with
particular aspects related to synthesis.

Topics
ESLsyn will focus on the five key tasks related to the design and
verification of complex, programmable electronic products:

-       The development of product architectures and specifications,
including the incorporation and configuration of IP

-       The mapping of applications to a product specification, including
hardware/software partitioning and processor optimization

-       The creation of pre-silicon, virtual hardware platforms for software
development

-       The determination/automation of a hardware implementation for that
architecture

-       The development of reference models for verifying the hardware
Furthermore, ESL syn addresses:

-       Cyber-Physical System/System/Platform related to ESL design flow

-       High-Level Synthesis, Behavioral Synthesis, Architectural Synthesis
for HW Design in cooperation with the ESL design flow

-       Embedded Software Synthesis that is used into the ESL design flow
The above list is not an exhaustive list of topics addressed by ESLsyn ;
contributions related to ESLsyn problems in general not listed here are
highly welcome. Submissions may be theoretical scientific papers, research
in progress, case studies, tool use cases and best practice, as well as
industry experiences.

Target Audience
This conference will provide an overview of existing and emerging solutions
provided by both industrial partners (EDA companies) and research
institutions in the domain of ESL synthesis. It will give an outline of
synthesis methods and tools available currently in the market and discuss
their applicability, performance, strengths and user experiences. Finally,
the event will create a discussion platform for experience exchange between
providers of synthesis technology and industry users, but also will be a
forum to discuss scientific concepts and paradigms for the future evolution
of synthesis methods.

Co-located with DAC
The Design Automation Conference (DAC) is the premier event for the design
of electronic circuits and systems, and for EDA and silicon solutions. Now
in its 49th year, DAC features a wide array of technical presentations, as
well as more than 200 of the leading electronics design suppliers in a
colorful, well-attended trade show that, literally, attracts stakeholders
from around the world.
DAC is where the IC Design and EDA ecosystem learns, networks, and does
business. DAC is also where the latest technical research is presented. DAC
covers all topics related to the design complex systems on chip: Embedded
System design and verification down to physical layout verification & test.

Important Information for Authors
Authors must follow the paper submission guidelines. Details can be found at
http://www.ecsi.org/eslsyn <http://www.ecsi.org/eslsyn/submissions> .
Questions, contact office@ecsi.org.
Important Dates

Paper Submission Deadline

Notification of Acceptance:

Full Final Paper Submission:

Copyright Forms:

Author Registration:

Presentations Submission + Presenter Bio


March 23, 2012

April 30, 2012

May 14, 2012

May 14, 2012

May 14, 2012

May 26, 2012



Demonstration Opportunities

ECSI Member Opportunities
Opportunities for ECSI members include:

·         Free of charge demonstration booths!

·         Free publicity of your organization!

·         Registration rates!
Contact us now to benefit from these opportunities or to find out more about
becoming an ECSI Member!


Program Committee

Shuvra Bhattacharyya, University of Maryland
Jens Brandt, Technical University of Kaiserslautern
Benjamin Carrion Schafer, NEC Corporation
Patricia Derler, UC Berkeley
Abdoulaye Gamatie, LIFL
Thierry Gautier, IRISA
Andreas Gerstlauer, University of Texas
Christoph Grimm, TU Vienna
Kim Grüttner, OFFIS
Yuko Hara-Azumi, Ritsumeikan University
Christian Haubelt, University of Erlangen-Nürnberg
Niraj K. Jha, Princeton University
Luciano Lavagno, Politecnico di Torino
Frédéric Mallet, INRIA
Adam Morawiec, ECSI
Steven Neuendorffer, Xilinx
Bernhard Niemann, Fraunhofer
Hiren Patel, University of Waterloo
Dumitru Potop-Butucaru, INRIA
Doemer Rainer, UC Irvine
Achim Rettberg, University of Oldenburg
Eric Rutten, INRIA
John Sanguinetti, Forte Design Systems
David Thomas, Imperial College London
Hiroyuki Tomiyama, Ritsumeikan University
Eugenio Villar University of Cantabria
Hiroaki Yoshida, University of Tokyo
Zhiru Zhang, UCLA


Follow ESLsyn on LinkedIn!

[http://www.ecsi.org/sites/default/files/images/LinkedIn_colour_lowres.jpg]<
http://www.linkedin.com/groups?about=&gid=4197998&trk=anet_ug_grppro>

Please, transfer this message to persons interested in this topic!
We apologise if you have received multiple copies of this message!
Please click here<http://www.ecsi.org/remove-mailing-list> if you wish to be
removed from this mailing list.
Please do not respond to this email address. Direct contact information can
be found at www.ecsi.org<http://www.ecsi.org> .





------ End of Forwarded Message

[toc] | [standalone]

Back to top | Article view | comp.parallel

csiph-web