Groups | Search | Server Info | Keyboard shortcuts | Login | Register [http] [https] [nntp] [nntps]

Groups > comp.parallel > #1122

WORKSHOP ON ENERGY-EFFICIENT NETWORK ON CHIP, MULTICORE AND MANYCORE ARCHITECTURES

Cross-posted to 2 groups.

Show all headers | View raw

---------------------------------------------------------------------------
-
CALL FOR PAPERS
---------------------------------------------------------------------------
-


The 1st  WORKSHOP ON ENERGY-EFFICIENT NETWORK ON CHIP, MULTICORE AND
MANYCORE ARCHITECTURES

 
Collocated with International Green Computing Conference (IGCC
<http://cm.wsu.edu/ehome/greencomputing14/159523/?&>), 2014
November 3-5, 2014
Dallas, TX, USA
---------------------------------------------------------------------------
-

General Information:
The E2NC Workshop will occupy one day of  the Fifth International Green
Computing Conference (IGCC 2014). There will be no separate registration
for the workshop. All workshop attendees will be registering for the IGCC
conference. All accepted papers will be published in workshop proceedings
together with other workshops by the IEEE Computer Society Press and the
IEEE online library.
For travel and registration information please refer to the main
conference IGCC 2014 website
<http://cm.wsu.edu/ehome/greencomputing14/159523/?&>.

Scope:
As part of the IEEE International Green Computing conference, a special
workshop termed Energy-efficient Network on Chip, Multicore and Manycore
Architectures will be organized to address various design aspects of power
efficient and dependable computing infrastructures. Computing machinery
around the world consumes staggering amounts of energy. The increasing
power consumption of Integrated Circuits has plagued the semiconductor
industry for years. Soaring power dissipations have proved to be the
limiting factor for increase in performance.  In the case of
high-performance manycore devices, such as GPUs, power consumption and
temperature issues prevent their mobile implementation. In addition, power
and temperature issues reduce the reliability of semiconductor devices.
Last, the communication and data exchange across these devices place extra
pressure on their power budget. This has necessitated paradigm shifts in
the IT and semiconductor industries at various levels. While major
research is dedicated towards designing energy-efficient hardware, the
aspect of reliability and dependability cannot be overlooked. This
workshop will encompass a broad range of topics related to power
efficiency and dependability of modern multicore, manycore and
heterogeneous chips. Its objective is to facilitate exchange of valuable
information and ideas among researchers and practitioners. The workshop
will consist of invited presentations and contributed peer-reviewed
research papers. The accepted contributions will appear in IEEE
proceedings as a part of the IGCC 2014 conference proceedings of 6 page
papers. The workshop will consist of invited presentations and contributed
peer-reviewed research papers.

The topics of interest include, but are not limited to, the following:
¨ Power and thermal management in multicore chips
¨ Sustainable multi-core architectures and networks-on-chip (NoCs)
¨ Emerging interconnect technologies
¨ Low power coding methods for NoCs
¨ Power-Efficient HPCs
¨ Energy-Efficient Sensor Networks
¨ Security and DoS issues for multicore chips
¨ Heterogeneous single-chip computers
¨ Temperature-aware task allocation

Author Information:
Full papers following the guidelines of the International Green Computing
Conference (http://cm.wsu.edu/ehome/greencomputing14/159534/?&) are
sought. Authors should select the Energy-efficient Network on Chip,
Multicore and Manycore Architectures ((E2NC) workshop when submitting
their papers. All submitted manuscripts will be reviewed and evaluated on
correctness, originality, technical strength, significance, quality of
presentation, and interest and relevance to the scope of the workshop.
Papers presented at the workshop will be published in the official
conference proceedings (through IEEE Digital Library) contingent on two
conditions: (1) at least one author of an accepted paper must register for
the conference at the time of the submission of the final manuscript and
(2) one of the authors must appear to present the paper at the workshop
---------------------------------------------------------------------------
-----

Important Dates:
 
Submission Due: 15th July 2014
Notification of Acceptance: 15th August 2014
Camera-ready paper due: 30th September 2014.
 
Workshop Organizers:
Amlan Ganguly, Rochester Institute of technology
Sonia Lopez-Alarcon, Rochester Institute of technology
 
Please direct questions regarding this workshop to Amlan Ganguly
(amlan.ganguly@rit.edu) or Sonia Lopez-Alarcon (slaeec@rit.edu).

Back to comp.parallel | Previous | Next | Find similar | Unroll thread

Thread

WORKSHOP ON ENERGY-EFFICIENT NETWORK ON CHIP, MULTICORE AND MANYCORE ARCHITECTURES Sonia Lopez Alarcon <slaeec@rit.edu> - 2014-07-07 14:09 +0000

csiph-web