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CfP: New Algorithms and Programming Models for the Manycore Era (Workshop @ HPCS 2014)

From Michael Bader <bader@in.tum.de>
Newsgroups comp.parallel, news.announce.conferences
Subject CfP: New Algorithms and Programming Models for the Manycore Era (Workshop @ HPCS 2014)
Date 2014-01-27 10:39 +0100
Organization A noiseless patient Spider
Message-ID <52E62944.8090201@in.tum.de> (permalink)

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++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
4th International Workshop on New Algorithms and
Programming Models for the Manycore Era
(APMM 2014)
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++

CALL FOR PAPERS
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
As part of The International Conference on
High Performance Computing & Simulation (HPCS 2014)

http://hpcs2014.cisedu.info or http://cisedu.us/rp/hpcs14

July 21 – July 25, 2014
The Savoia Hotel Regency
Bologna, Italy

Submission Deadline: March 11, 2014 (full paper, short papers)

SCOPE AND OBJECTIVES
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
With multi- and many-core based systems, performance increase on the
microprocessor side will continue according to Moore's Law, at least
in the near future. However, the already existing performance limitations
due to slow memory access are expected to get worse with multiple cores
on a chip, and complex hierarchies of cache memory will make it hard for
users to fully exploit the theoretically available performance. In
addition, the increasingly hybrid and hierarchical design of compute
clusters and high-end supercomputers, as well as the use of accelerator
components (GPGPUs by AMD and NVIDIA, Intel Xeon Phi, Intel SCC, integrated
GPUs etc.) add further challenges to efficient programming in HPC 
applications.

Therefore, compute and data intensive tasks can only benefit from the 
hardware's
full potential, if both processor and architecture features are taken into
account at all stages - from the early algorithmic design, via appropriate
programming models, up to the final implementation.

The APMM Workshop topics of interest include (but are not limited to)
the following:

- Hardware-aware, compute- and memory-intensive simulations of
real-world problems in computational science and engineering
(for example, from applications in electrical, mechanical,
civil, or medical engineering).
- Manycore-aware approaches for large-scale parallel simulations
in both implementation and algorithm design, including scalability
studies.
- Parallelisation on HPC platforms; esp. platforms with hierarchical
communication layout, multi-/many-core platforms, NUMA architectures,
or accelerator components (Intel Xeon Phi, NVIDIA and AMD GPU, Tilera,
FPGA, integrated GPUs (such as AMD APUs or Intel Haswell/Ivy Bridge)).
- Parallelisation with appropriate programming models and tool support
for multi-core and hybrid platforms.
- concepts for exploiting emerging vector extensions of instruction sets
- Software engineering, code optimisation, and code generation strategies
for parallel systems with multi-core processors.
- Tools for performance and cache behavior analysis (including cache
simulation) for parallel systems with multi-core processors.
- Performance modelling and performance engineering approaches for
multi-thread and mutli-process applications.


INSTRUCTIONS FOR PAPER SUBMISSIONS:
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
See the workshop website on
http://cisedu.us/rp/hpcs14/2-conference/workshops/workshop-06-apmm
Accepted papers will be published in the conference proceedings.

IMPORTANT DATES
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Paper Submissions Deadline: ------------------------- March 11, 2014
Acceptance Notification: ---------------------------- April 08, 2014
Camera Ready Papers and Registration Due by: -------- May 06, 2014
Conference Dates: ---------------------------------- July 21 – 25, 2014


WORKSHOP STEERING COMMITTEE
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Michael Bader, Technische Universität München, Germany
Alexander Heinecke, Technische Universität München, Germany
Carsten Trinitis, Technische Universität München, Germany
Josef Weidendorfer, Technische Universität München, Germany

WORKSHOP ORGANIZERS
++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
Alexander Heinecke
Technische Universität München, Germany
Phone: +49 89 289 18619
Fax: +49 89 289 18607
Email: heinecke@in.tum.de

Sven-Bodo Scholz
Heriot-Watt University Edinburgh, United Kingdom
Phone: +44 (0) 131 451 3814
Fax: +44 (0)
Email: s.scholz@hw.ac.uk



-- 
Prof. Dr. Michael Bader             Email: bader@in.tum.de
Department of Informatics           Tel.:  089/35831-7810
Technische Universität München      WWW:   http://www5.in.tum.de/~bader

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CfP: New Algorithms and Programming Models for the Manycore Era (Workshop @ HPCS 2014) Michael Bader <bader@in.tum.de> - 2014-01-27 10:39 +0100

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